如何为 kernel 模块 makefile 添加包含路径

Question

How do I add an include path for kernel module makefile? I want to include "test_kernel.h" in test_module.c. the "test_kernel.h" resides in other directory "inc" I tried in the following solution in my Makefile but it does not work:

obj-m += test_module.o

test_module:
    $(MAKE) -C "$(LINUX_DIR)" -Iinc $(MAKE_OPTS) modules

Answer 1

You should make use of EXTRA_CFLAGS in your Makefile . Try something on these lines:

obj-m += test_module.o
EXTRA_CFLAGS=-I$(PWD)/inc

test_module:
    $(MAKE) -C "$(LINUX_DIR)" $(MAKE_OPTS) modules

See section 3.7 Compilation Flags section here .
Hope this helps!

Answer 2

are you sure you correctly specified the include in your file?

eg:

#include "inc/something.h"

instead of

#include <inc/something.h>

Answer 3

For me, many trials have failed, until one of them has succeeded. Using $(src) in the path will do it with ccflags-y , for instance:

# Include Paths
ccflags-y       += -I$(src)/../../lib/include 

For a directory "/lib/include" that is two levels up from the source folder.

This is driven from the statement in Kernel.org

Always use $(src) when referring to files located in the src tree Specially, if your source code is in directory that is outside the Linux Kernel Tree.

Answer 4

-I is a GCC flag, not a Make flag. ¹ You need to pass a variable down to your "sub" Make process; perhaps something like this:

$(MAKE) -C "$(LINUX_DIR)" CPPFLAGS="-Iinc" $(MAKE_OPTS) modules

where CPPFLAGS is a standard Make variable that's used in the implicit rules. Feel free to use your own variable instead, and ensure it's used appropriately in the sub-make.

The Make manual gives more details on communicating variables between Make instances: http://www.gnu.org/software/make/manual/make.html#Variables_002fRecursion .

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_{1. Actually, it is also a Make flag, but for something completely unrelated.}