确定如何实现OpenMP原子指令

Question

A compiler that implements the OpenMP standard may, but is not obliged to, exploit special hardware instructions to make certain memory updates following a #pragma omp atomic directive atomic, avoiding expensive locks. According to http://gcc.gnu.org/onlinedocs/gccint/OpenMP.html , GCC implements an atomic update as follows:

Whenever possible, an atomic update built-in is used. If that fails, a compare-and-swap loop is attempted. If that also fails, a regular critical section around the expression is used.

1. How can I determine which of the three is actually used on a given machine and GCC version? Is there some verbosity option for GCC that I can set to find out without having to profile my program or look a the generated bytecode?

2. Is there some documentation listing CPUs/architectures that provide atomic addition/increment/etc instructions, allowing me to predict the outcome for a given machine?

I'm using GCC versions 4.2 to 4.6 on a variety of different machines.

Answer 1

You may look at the intermediate tree representations with the -fdump-tree-all option. Given that option, GCC writes a set of files at several intermediate steps and one can observe the successive transformations applied to the tree. The .ompexp file is of particular interest here, since it contains the tree just after the OpenMP expressions were expanded into their concrete implementations.

For example, the block inside the parallel region in the following simple code:

int main (void)
{
    int i = 0;

    #pragma omp parallel
    {
       #pragma omp atomic
       i++;
    }

    return i;
}

is transformed by GCC 4.7.2 on 64-bit Linux into:

;; Function main._omp_fn.0 (main._omp_fn.0, funcdef_no=1, decl_uid=1712, cgraph_uid=1)

main._omp_fn.0 (struct .omp_data_s.0 * .omp_data_i)
{
  int D.1726;
  int D.1725;
  int i [value-expr: *.omp_data_i->i];
  int * D.1723;
  int * D.1722;

<bb 2>:
  D.1722_2 = .omp_data_i_1(D)->i;
  D.1723_3 = &*D.1722_2;
  __atomic_fetch_add_4 (D.1723_3, 1, 0);
  return;

}

which finally ends into:

00000000004006af <main._omp_fn.0>:
  4006af:       55                      push   %rbp
  4006b0:       48 89 e5                mov    %rsp,%rbp
  4006b3:       48 89 7d f8             mov    %rdi,-0x8(%rbp)
  4006b7:       48 8b 45 f8             mov    -0x8(%rbp),%rax
  4006bb:       48 8b 00                mov    (%rax),%rax
  4006be:       f0 83 00 01             lock addl $0x1,(%rax)
  4006c2:       5d                      pop    %rbp
  4006c3:       c3                      retq

As for the second question, it might also depend on how GCC was built.

Answer 2

GCC will define macros

#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1

if the respective operations are available.

In general, one can always expect to have compare and swap (either in the form of a CAS or LL/SC) on any architecture, which supports multiple processors.

In addition, on x86 there's atomic increment and decrement.