我可以为C项目重新生成一个makefile，具有正确的链接顺序和依赖关系吗？

Question

I have source code I last worked on in the late 90's-2000 and have it all backed up, apart from the makefile (yes berate away, bad backups are almost as good as no backups): so... I am wondering if there is any automated way to generate the makefile or a good way to analyse the dependencies quickly?

Specifically I am looking for:

• a tool which could analyse the dependencies and correct the link order for me.
• if such does not exist, then advice is greatly appreciated as to how to best approach this problem from someone who has had similar problem(s) in the past
• failing either of the above two options, I think the best approach is to create an analysis/make-file creation tool which can automatically generate the dependencies order for linking (I have held off on this approach as time is always in short supply to squeeze in another project).

The reason for this quest for help/advice is that the code-base is 300,000 lines of code (excluding comments) and spans hundreds of C/O files, and as often as I have tried creating a make-file by hand, it frustrates and confounds, hence my last attempt to seek help and ask in here.

For reference: I have tried Cmake , AutoMake, GenMake and similar tools in the past to generate the makefile, all to no avail, as the dependencies are horrendous.

---

Generic makefile script

As it may be of use to others, here is the makefile I usually use for less convoluted C and C++ projects, as it saves me having to worry about creating a new one every time:

$(VERBOSE).SILENT:
PROGRAMNAME = prog
CC = gcc
CC += -c
CPP = g++
CPP += -c
ASM = nasm
ASM += -f elf -d ELF_TYPE
LD = g++
OBJFILES = $(patsubst %.c,%.o,$(wildcard *.c))
OBJFILES += $(patsubst %.s,%.o,$(wildcard *.s))
OBJFILES += $(patsubst %.cpp,%.o,$(wildcard *.cpp))

all: $(PROGRAMNAME)

clean:
    @echo "Cleaning object files"
    @echo "    rm -f     *.o"
    rm -f *.o
    @echo "Cleaning backups"
    @echo "    rm -f     *~"
    rm -f *~
    @echo "Removing program file"
    @echo "    rm -f     "$(PROGRAMNAME)
    rm -f $(PROGRAMNAME)

%.o: %.s
    @echo "Assembling ASMs "$@
    @echo "    ASM       "$<
    $(ASM) $<

%.o: %.c
    @echo "(C)ompiling "$@
    @echo "    CC        "$<
    $(CC) $<

%.o: %.cpp
    @echo "(C++)ompiling "$@
    @echo "    CPP       "$<
    $(CPP) $<

$(PROGRAMNAME): $(OBJFILES)
    @echo "Get ready...."
    @echo "Linking "$@
    @echo "    LD        -o "$(PROGRAMNAME)"        "$(OBJFILES)
    $(LD) -o $(PROGRAMNAME) $(OBJFILES)
    @echo "Cry if it worked! Scream swear and cry if it did not..."

strip: $(PROGRAMNAME)
    @echo "Stripping "$(PROGRAMNAME)
    echo -n "Size of "$(PROGRAMNAME)" before stripping is "
    ls -sh $(PROGRAMNAME) | cut -d' ' -f1
    @echo "    Stripping     "$(PROGRAMNAME)
    strip $(PROGRAMNAME)
    echo -n "Size of "$(PROGRAMNAME)" after stripping is "
    ls -sh $(PROGRAMNAME) | cut -d' ' -f1

nothing:
    @echo "Nothing to do; see you later - I'm going home!!!"
    @echo "Hey, try some of these:"
    @echo "make all   - this would be the one you want"
    @echo "make strip - does not work in the real world, only in computers"
    @echo "make clean - will help clean your mind up"

Answer 1

gcc＆clang可以生成依赖关系，请参阅高级自动依赖关系生成 ，这不会解决整个问题但会对您有所帮助。

Answer 2

您正在寻找MIT， makedepend的经典Unix工具。

Answer 3

On a linux/unix system:

find . -name "*.c" -print > sources find . -name "*.c" -print > sources will give you a list of all the sources.

find . -name "*.c" -print|sed s/\\.c/\\.o > objects find . -name "*.c" -print|sed s/\\.c/\\.o > objects should give you a list that you can stick "OBJECTS=" in front of [maybe manually add some linebreaks].

cat sources|xargs gcc -M > myprog.deps should give you a list of header dependencies that you can include myprog.deps in your makefile. [1]

Now all you need is TARGET = myprog # Whatever you call your program!

OBJECTS = ... # from "objects" file above. 
SOURCES = ... # from "sources" file above

INCLUDES = -I subdir1 -I subdir2 ...     # include directories used by this product

CFLAGS = ... ${INCLUDES} # Some suitable settings
CC = gcc
LD = ${CC}
LDFLAGS =  ...    # I don't know what this needs to be - usually nothing complicated.

all: ${TARGET}

clean:
    rm -f ${TARGET} ${OBJECTS}

${TARGET}: ${OBJECTS}
    ${LD} -o $@ ${OBJECTS}

.c.o:
    ${CC} -o $@ $<

That should have MOST of the hard work done, unless you have to build internal tools or your many source files don't actually produce one final binary of course - in the latter case, you'll probably have to search for "main" and go through the above steps for each executable - you can still use a top-level Makefile and use include of the intermediate ones.

[1] You could add to the makefile - particularly if your project produces many different executables.

myprog.deps: ${SOURCES}
    ${CC} -MM ${SOURCES} > myprog.deps

include myprog.deps

Answer 4

Thanks for the great response: concise and very informational. Based on the answers I am now using a mixture of manual effort and GNU AutoMake (the modern successor to makedepend) to try recompiling, and so far seems to be quite effective.

Then shall come the fun and games of porting to OO code in C++...that's a task I would gladly avoid but needs must.

Thanks again!