VHDL：std_logic_vector左移和右移運算符？

Question

任何人如何在STD_LOGIC_VECTor上執行VHDL的右移或左移...

它行不通，為什么？

AN <= "0001";        
CounterProcess: process(CLK,Switch)
    begin
    if rising_edge(CLK) then
        if prescaler < limit then 
            prescaler <= prescaler + 1;
            else
                prescaler <= (others => '0'); 
                counter <= counter + 1;
                AN sll 1;
        end if;
    end if; 
    end process;
    An <= anode;

    Segment <= counter; 

    end Behavioral;

我收到錯誤消息：sll在這種情況下不能有這樣的操作數。 但是，可以在哪種情況下使用它？如何執行左移？

這些是我的包括：

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

是不是執行我的左移操作所需的那個？

---

完整的代碼

entity Main is
PORT(
        CLK: in std_logic;
        LED: out std_logic_vector (7 downto 0);
        Switch: in std_logic_vector(7 downto 0);
        Segment: out std_logic_vector (7 downto 0); 
        AN: out std_logic_vector (3 downto 0) 
        );

end Main;


architecture Behavioral of Main is
signal counter: std_logic_vector (7 downto 0);
signal prescaler:  std_logic_vector(25 downto 0);
signal limit: std_logic_vector (25 downto 0);
signal anode: std_logic_vector (3 downto 0);
begin
AN <= "0001";

ScalerChoice: Process(switch)
begin
CASE Switch IS
when "00000001" => limit <= "10111110101111000010000000"; -- 1 Hz;
when "00000010" => limit <= "00111111100101000000101011"; -- 3 HZ
When "00000100" => limit <= "00010011000100101101000000"; -- 10 Hz
when "00001000" => limit <= "00000111101000010010000000"; -- 25 Hz
When "00010000" => limit <= "00000011110100001001000000"; -- 50 Hz; 
when "00100000" => limit <= "00000001111010000100100000"; -- 100 hz
when others => limit <=      "00000000000000000000000001"; -- 50 MHz
end case;
end process;


CounterProcess: process(CLK,Switch)
begin
if rising_edge(CLK) then
    if prescaler < limit then 
        prescaler <= prescaler + 1;
        else
            prescaler <= (others => '0'); 
            counter <= counter + 1;
            AN sll AN 1;
    end if;
end if; 
end process;

Segment <= counter; 

end Behavioral;

Answer 1

除了trumpetlicks所說的以外，請改用這些軟件包。 確保啟用VHDL-2008開關。 另外，請先與您的FPGA供應商聯系，因為它們需要VHDL-2008更新：

library IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use ieee.numeric_std.all;
   use ieee.numeric_std_unsigned.all;

以上軟件包均為IEEE標准。 程序包STD_LOGIC_ARITH和std_logic_unsigned不是IEEE標准。 還要注意， numeric_std和STD_LOGIC_ARITH彼此沖突，因此很難（超出基本用法）使用signed和unsigned類型。 請注意， std_logic_unsigned與numeric_std_unsigned沖突。 因此，如果您的綜合工具支持numeric_std_unsigned ，我建議改用它。 此外，如果沒有，則應提交針對它的錯誤報告。

Answer 2

編輯1：

您的代碼使用復位邏輯進行編輯，請注意將RESET信號添加到端口列表，刪除了該值的異步線路設置，將RESET到CounterProcess進程的靈敏度列表中，並添加了if(RESET = '1')行，而變化if到elsif ，以及你的變速線的變更：

我實際上不知道您的An <= Anode線在做什么，並且相信這也是錯誤的。

entity Main is PORT(
    RESET:   in  std_logic;
    CLK:     in  std_logic;
    LED:     out std_logic_vector(7 downto 0);
    Switch:  in  std_logic_vector(7 downto 0);
    Segment: out std_logic_vector(7 downto 0); 
    AN:      out std_logic_vector(3 downto 0)
);
end Main;

architecture Behavioral of Main is
signal counter:   std_logic_vector(7  downto 0);
signal prescaler: std_logic_vector(25 downto 0);
signal limit:     std_logic_vector(25 downto 0);
signal anode:     std_logic_vector(3  downto 0);

begin

ScalerChoice: Process(switch)
begin
CASE Switch IS
when "00000001" => limit <= "10111110101111000010000000"; -- 1 Hz;
when "00000010" => limit <= "00111111100101000000101011"; -- 3 HZ
When "00000100" => limit <= "00010011000100101101000000"; -- 10 Hz
when "00001000" => limit <= "00000111101000010010000000"; -- 25 Hz
When "00010000" => limit <= "00000011110100001001000000"; -- 50 Hz; 
when "00100000" => limit <= "00000001111010000100100000"; -- 100 hz
when others => limit <=     "00000000000000000000000001"; -- 50 MHz
end case;
end process;


CounterProcess: process(RESET, CLK, Switch)
begin
    if(RESET = '1') then
        AN <= "0001";
    elsif rising_edge(CLK) then
        if prescaler < limit then 
            prescaler <= prescaler + 1;
        else
            prescaler <= (others => '0'); 
            counter <= counter + 1;
            AN <= std_logic_vector(unsigned(AN) sll 1);
        end if;
    end if;
end process;

An <= anode;
Segment <= counter; 

end Behavioral;

您需要編寫當前具有的行：

AN sll 1;

如

AN <= AN sll 1;

請記住， AN本質上就像一個變量，需要“設置”。 就像你上面的線

counter <= counter + 1;