[英]How to take samples using fpga?
I want to take samples of digital data coming externaly to FPGA spartan 3. I want to take 1000 samples/sec initially. 我想从FPGA spartan 3外部获取数字数据的样本。我最初希望每秒获取1000样本。 How to select a clock frequency in vhdl coding?
如何在VHDL编码中选择时钟频率?
Thanks. 谢谢。
Do not use a counter to generate a lower frequency clock signal. 不要使用计数器来产生低频时钟信号。
Multiple clock frequencies in an FPGA cause a variety of design problems, some of which come under the heading of "advanced topics" and, while they can (if necessary) all be dealt with and solved, learning how to use a single fast clock is both simpler and generally better practice (synchronous design). FPGA中的多个时钟频率会导致各种设计问题,其中一些属于“高级主题”,尽管可以(如有必要)解决所有这些问题,但了解如何使用单个快速时钟是非常重要的。既更简单又通常更好的做法(同步设计)。
Instead, use whatever fast clock your FPGA board provides, and generate lower frequency timing signals from it, and - crucially - use them as clock enables, not clock signals. 相反,请使用FPGA板提供的任何快速时钟,并从中生成较低频率的定时信号,并且-至关重要的是-将它们用作时钟使能,而不是时钟信号。
DLLs, DCMs, PLLs and other clock managers do have their uses, but generating 1 kHz clock signals is generally not a good use, even if their limitations permit it. DLL,DCM,PLL和其他时钟管理器确实有其用途,但即使它们的限制允许,生成1 kHz时钟信号通常也不是一个好方法。 This application is just crying out for a clock enable...
这个应用程序只是在呼吁时钟启用...
Also, don't mess around with magic numbers, let the VHDL compiler do the work! 另外,不要弄乱魔术数字,让VHDL编译器完成工作! I have put the timing requirements in a package, so you can share them with the testbench and anything else that needs to use them.
我已将时序要求打包在一起,因此您可以将它们与testbench以及需要使用它们的其他任何东西共享。
package timing is
-- Change the first two constants to match your system requirements...
constant Clock_Freq : real := 40.0E6;
constant Sample_Rate : real := 1000.0;
-- These are calculated from the above, so stay correct when you make changes
constant Divide : natural := natural(Clock_Freq / Sample_Rate);
-- sometimes you also need a period, e.g. in a testbench.
constant clock_period : time := 1 sec / Clock_Freq;
end package timing;
And we can write the sampler as follows: (I have split the clock enable out into a separate process to clarify the use of clock enables, but the two processes could be easily rolled into one for some further simplification; the "sample" signal would then be unnecessary) 我们可以编写采样器,如下所示:(我将时钟使能分成了一个单独的过程,以阐明时钟使能的使用,但是可以将这两个过程轻松合并为一个,以进行进一步简化;“采样”信号将然后是不必要的)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.timing.all;
entity sampler is
Port (
Clock : in std_logic;
Reset : in std_logic;
ADC_In : in signed(7 downto 0);
-- signed for audio, or unsigned, depending on your app
Sampled : out signed(7 downto 0);
);
end sampler;
architecture Behavioral of Sampler is
signal Sample : std_logic;
begin
Gen_Sample : process (Clock,Reset)
variable Count : natural;
begin
if reset = '1' then
Sample <= '0';
Count := 0;
elsif rising_edge(Clock) then
Sample <= '0';
Count := Count + 1;
if Count = Divide then
Sample <= '1';
Count := 0;
end if;
end if;
end process;
Sample_Data : process (Clock)
begin
if rising_edge(Clock) then
if Sample = '1' then
Sampled <= ADC_In;
end if;
end if;
end process;
end Behavioral;
The base clock must be based on an external clock, and can't be generated just through internal resources in a Spartan-3 FPGA. 基本时钟必须基于外部时钟,并且不能仅通过Spartan-3 FPGA中的内部资源生成。 If required, you can use the Spartan-3 FPGA Digital Clock Manager (DCM) resources to scale the external clock.
如果需要,您可以使用Spartan-3 FPGA数字时钟管理器(DCM)资源来缩放外部时钟。 Synthesized VHDL code in itself can't generate a clock.
合成的VHDL代码本身无法生成时钟。
Once you have some base clock at a higher frequency, for example 100 MHz, you can easily divide this down to generate an indication at 1 kHz for sampling of the external input. 一旦有了一些较高频率(例如100 MHz)的基本时钟,就可以轻松地对其进行分频,以产生1 kHz的指示以用于外部输入的采样。
It depends on what clock frequency you have available. 这取决于您可用的时钟频率。 If you have a 20MHz clock source, you need to divided it by 20000 in order to get 1KHz, you can do it in VHDL or use a DCM to do this.
如果您有20MHz的时钟源,则需要将其除以20000才能获得1KHz,您可以在VHDL中执行此操作,也可以使用DCM进行此操作。
This is from an example on how to create a 1kHz clock from a 20MHz input: 这是一个有关如何从20MHz输入创建1kHz时钟的示例:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk20Hz is
Port (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end clk200Hz;
architecture Behavioral of clk20Hz is
signal temporal: STD_LOGIC;
signal counter : integer range 0 to 10000 := 0;
begin
frequency_divider: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = 10000) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral;
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