如何编写更简洁的Makefile（带有sub Makfile）

Question

When I do practice , I have a practice path.

Under this path , I have an Include path named myInclude (I have some useful function is this folder and I always use it.)

And a code path named symbol_try .I always make add new folder (with ac file and main function in it) in symbol_try and compile it.

Each time I have to compile it by gcc in terminal .Its a boring work , so I write a Makefile.

Here is an example:

the main Makefile in practice path:

FOBJS=
include myInclude/Rule.mk
include symbol_try/codeList_13.1/Rule.mk
symbol:$(FOBJS)                   <==What exactly I what . A executable file.
    gcc -o symbol $(FOBJS) -pthread -lpthread

subsystem:
    cd myInclude/ && $(MAKE)
    cd symbol_try/codeList_13.1/ &&$(MAKE)
clean:
    rm -rf symbol   

In the myInclude/Rule.mk

FOBJS+=myInclude/otherFunction.o myInclude/error.o \
       myInclude/unit.o myInclude/unitTest.o\

In the symbol_try/codeList_13.1/Rule.mk

FOBJS+=symbol_try/codeList_13.1/codeList_13.1.o

In myInclude/Makefile:

    OBJS=otherFunction.o error.o unit.o unitTest.o
    ALL:$(OBJS)
    .PHONY:ALL
    $(OBJS):%.o:%.c
        gcc -c $< -o $@

    clean :
        otherFunction.o error.o unit.o

In symbol_try/codeList_13.1/Makefile:

codeList_13.1.o:codeList_13.1.c
    gcc -c codeList_13.1.c

Well.That can work. But as you see , I have to write a Rule.mk(to initialize the FOBJS) and a Makefile for each folder.

I am new for make , I want find a way more concise , witch I only need write one Makefile for each folder and a main Makefile. No Rule.mk any more .

PS: I always change the code in myInclude ,so I don't want to build it a library.

Thanks for any help.

Answer 1

Here's one way you can do it with just one Makefile:

CC        = gcc
CPPFLAGS += -I myInclude/                             (1)
CFLAGS   += -std=c99 -Wall                            (2)
VPATH     = myInclude/ \                              (3)
            symbol_try/codeList_13.1/

symbol: otherFunction.o error.o unit.o unitTest.o codeList_13.1.o  (4)
    $(CC) -o $@ $^                                    (5)

.PHONY : clean
clean:
    rm -f symbol *.o

Note that make knows how to build C files and has some standard macros: CC, CPPFLGAS, CFLAGS

1. Add the include paths of your headers. You presumably have some headers for the individual object files in the myInclude directory.
2. Put the compiler flags here.
3. Add the paths to the source files you want to build.
4. List the object files that the executable depends upon
5. As there is no file called symbol.c you need to tell make how to create symbol.o with a rule. $@ means the target ('symbol', here), and $^ means all of the prerequisites (the object files listed).

Here's a list of all of the files in my test directories for this:

$ find . -type f
.
./Makefile
./myInclude/error.c
./myInclude/header.h
./myInclude/otherFunction.c
./myInclude/unit.c
./myInclude/unitTest.c
./symbol_try/codeList_13.1/codeList_13.1.c

And the build output:

$ make
gcc -std=c99 -Wall -I myInclude/  -c -o otherFunction.o myInclude/otherFunction.c
gcc -std=c99 -Wall -I myInclude/  -c -o error.o myInclude/error.c
gcc -std=c99 -Wall -I myInclude/  -c -o unit.o myInclude/unit.c
gcc -std=c99 -Wall -I myInclude/  -c -o unitTest.o myInclude/unitTest.c
gcc -std=c99 -Wall -I myInclude/  -c -o codeList_13.1.o symbol_try/codeList_13.1/codeList_13.1.c
gcc -o symbol otherFunction.o error.o unit.o unitTest.o codeList_13.1.o

Answer 2

Why don't you create a library from the objects in myInclude and do the linking in the Makefile in your code path (symbol_try/codeList_13.1). The latter is better anyway because the needed libraries ( -pthread -lpthread in your case) might change as well for some other code. The main Makefile now would have got nothing to do but call make in all needed subdirectories.

Answer 3

In each folder have a makefile with

    SOURCES=sample.c sampletest.c

    OBJECTS=$(SOURCES:%.c=$(OBJDIR)/%.o)

    all: $(OBJECTS)

    $(OBJDIR)/%.o: %.c
        $(CC) $(CFLAGS) -o $@ $<

In the root directory of a project, create a makefile with a rule to compile every sub-folder like the below.

    Dirs= path-to-rootdir
    objs:
    set -e ; \
    for i in $(Dirs) ; do \
      $(MAKE) CC="$(CC)" CFLAGS="$(CFLAGS_MODULE)" LDFLAGS="$(LDFLAGS)"  OBJDIR="$(OBJDIR)" -C $$i; \
done

And then you could use it build the executable by adding a rule

   EXE: objs
    $(CC)  -L./Path1 $(LIB_PATH)  -llib1  -o $(EXE_NAME) $(wildcard $(OBJDIR)/*.o) 

Hope this helps!!!