如何编写“选择性” Makefile？

Question

noob question here.

I have a directory with a lot of .c files, they're basicely libc functions that I code myself as an exercice.

I write a little main() in these files to test the functions, and I want to write a Makefile that allow me to compile only the file I want to test, for exemple:

make memset.c

And get only the executable of the code wrote in memset.c.

I tried to do something like this:

CC = gcc
CFLAGS = -Wall -Wextra -pedantic

all : %.o
    $(CC) $(CFLAGS) $<
%.o : %.c
    $(CC) $(CFLAGS) $< -c -o $@

But obviously it doens't work. I don't what to put in place of the "all". I know it's very basic, but I didn't manage to do it, and I did research but didn't find an answer to this specific question.

Thanks in advance for your help.

Answer 1

If you do make -n -p you get a dump of all of the built-in rules in make. In GNU Make 4.1, this includes:

%: %.o
#  recipe to execute (built-in):
        $(LINK.o) $^ $(LOADLIBES) $(LDLIBS) -o $@

So you might just needs a % in your makefile where you currently have all .

You also might find that you don't need those rules which are already built in. Suppose you have three C files, each with a main() as you specify: abs.c , div.c and fmax.c . Your Makefile needs to be no more than two lines:

CFLAGS = -Wall -Wextra -pedantic
all: abs div fmax

which would then allow you to do make abs to make the abs executable, and make all to make them all.

Answer 2

You can define static pattern rules to build the object files and the executables and then invoke make with the name of the executable you want as the goal:

CC     = gcc
CFLAGS = -Wall -Wextra -pedantic

SRC := $(wildcard *.c)
OBJ := $(patsubst %.c,%.o,$(SRC))
EXE := $(patsubst %.c,%,$(SRC))

.PHONY: all obj

all: $(EXE)

obj: $(OBJ)

$(EXE): %: %.o
    $(CC) $(LDFLAGS) $< -o $@

$(OBJ): %.o: %.c
    $(CC) $(CFLAGS) $< -c -o $@

.PHONY: clean

clean:
    rm -f $(OBJ) $(EXE)

Then:

$ make memset.o

builds only memset.o ,

$ make memset

builds only memset (and memset.o if needed),

$ make obj

builds all object files,

$ make # or make all

builds all executables (and object files if needed), and

$ make clean

deletes all executables and object files.

Answer 3

With wildcard , you can achieve what you want.

Note that if each program depends on only one .c file, you don't need %.o rules:

CC = gcc
CFLAGS = -Wall -Wextra -pedantic

SRC  := $(wildcard *.c)
EXEC = $(SRC:%.c=%)

all: $(EXEC)

%: %.c
       $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS)

And just invoke this way for instance:

make memset

Answer 4

You already have most you to compile the executable selectively:

CC = gcc
CFLAGS = -Wall -Wextra -pedantic

%.o : %.c
    $(CC) $(CFLAGS) $< -c -o $@
% : %.o
    $(CC) $(LDLAGS) $< -o $@

Then you just need to call make with the target you want, the executable:

make select

If you have several sets of executable with different flags, you can use:

EX0 = drink clean
${EXE0}: % : %.o
        $(CC) $(LDLAGS) -lwater $< -o $@
EX1 = burn melt
{EX1}: % : %.o
        $(CC) $(LDLAGS) -lfire  $< -o $@