VHDL转换操作

Question

I have 2 std_logic_vector inputs (Operand1 and Operand2) and i am trying to shift Operand1 by the values in Operand2 and store it in a std_logic_vector output (Output1)

Output1 <= std_logic_vector(unsigned(Operand1) srl to_integer(unsigned(Operand2)));

Output1 <= std_logic_vector(unsigned(Operand1) sll to_integer(unsigned(Operand2)));

Output1 <= std_logic_vector(unsigned(Operand1) sra to_integer(unsigned(Operand2)));

I am able to get the first 2 lines to work, however the line with the sra returns this error "sra can not have such operands in this context." Can anybody tell me if there is anything i am doing wrong.

Answer 1

From the comments it sounds like some of your signals are of type std_logic_vector and some are of type bit_vector, and without posting the declarations you are giving us a merry guessing game which is which.

So what is wrong?

1. There isn't enough info in the question. Post the relevant declarations.

2. The design is clearly wrong. A big part of the design is the data types used, and these look to be badly chosen.

We don't have enough info peering through this tiny window onto the design to be able to fix it; so this is a wild guess :

Make Operand 1 Unsigned and operand 2 Integer or better Natural (if negative values would be a mistake) and the implementation will be much smoother, cleaner, simpler, easier to understand. And catch many more bugs earlier. These types are synthesisable and can be used as ports or signals or components in records (structs) if you desire.

And realise that SRA is not part of the VHDL language. It's a function, declared in some library.

So if you decide Operand1 is unsigned and Operand2 is natural (a subtype of integer) you can look at the numeric_std package and see if there is a declaration of SRA accepting those parameter types and returning the type you want.

And if there isn't, there is nothing stopping you writing your own (which could be as simple as a wrapper calling the SRA you found, and converting the parameter types as you need). It will be just as much part of the VHDL language as the original one.

A package of useful functions and helpers that you have written will prove useful on future VHDL projects.

Answer 2

Try changing the last line to:

Output1 <= std_logic_vector(unsigned(Operand1) sra to_integer(signed(Operand2)));

ie use signed instead of unsigned