与 Verilog 仿真实时通信

Question

I hope to realtime communicate with verilog simulation, just like I type a number at some where and verilog simulation can read it and show it. So I find a way that use read/write a file to communicate. First I write ac program to scanf what I type in the terminal and realtime change a number in a specific file. Then I thought if the verilog keep fscanf the file, it can communicate. I wrote the verilog code below, it works but not very good. If I type 1 ~ 9 each for one second, it will lose about six numbers. I hope all the number I type can be read by verilog. I use ncverilog to compile. Can anyone tell me how to fix my verilog or there are another way to communicate with verilog. Thanks a lot.

module testbench;
reg [100:0] t1;
reg [100:0] t2;
integer in;
initial begin
   t1=0;t2=0;
end
always begin
   in = $fopen("in.txt","r");
   $fscanf(in,"%d",t1);
   if(t1!=t2) begin
      $display("%d",t1);
      t2=t1;
   end
   $fclose(in);
end
endmodule

Answer 1

This is certainly possible, but I think attempting to use a file for communication is the wrong approach. You are bound to run into race conditions and other issues with file/IO buffers.

Alternatively, you could use the Verilog PLI to have your C program send data to the simulation on a certain event, say when the Enter key is pressed.

Answer 2

Old question, related answer. You can see bidirectiona file io here in my uart sim.

https://github.com/Johnlon/spam-1/blob/master/verilog/uart/um245r.v

On unix you can use a unix domain socket and treat like a terminal with a little work.