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计算3级缓存的实际/有效CPI

[英]Calculating actual/effective CPI for 3 level cache

(a) You are given a memory system that has two levels of cache (L1 and L2). (a)为您提供了具有两个高速缓存级别(L1和L2)的内存系统。 Following are the specifications: 以下是规格:

  • Hit time of L1 cache: 2 clock cycles L1缓存的命中时间:2个时钟周期
  • Hit rate of L1 cache: 92% L1缓存的命中率:92%
  • Miss penalty to L2 cache (hit time of L2): 8 clock cycles L2高速缓存的未命中罚款(L2的命中时间):8个时钟周期
  • Hit rate of L2 cache: 86% L2缓存的命中率:86%
  • Miss penalty to main memory: 37 clock cycles 未命中损失到主存储器:37个时钟周期
  • Assume for the moment that hit rate of main memory is 100%. 暂时假设主存的命中率为100%。

Given a 2000 instruction program with 37% data transfer instructions (loads/stores), calculate the CPI (Clock Cycles per Instruction) for this scenario. 给定一个2000指令程序,该指令程序具有37%的数据传输指令(装载/存储),请计算此方案的CPI(每个指令的时钟周期)。

For this part, I calculated it like this (am I doing this right?):

(m1: miss rate of L1, m2: miss rate of L2)

AMAT = HitTime_L1 + m1*(HitTime_L2 + m2*MissPenalty_L2)
CPI(actual) = CPI(ideal) + (AMAT - CPI(ideal))*AverageMemoryAccess

(b) Now lets add another level of cache, ie, L3 cache between the L2 cache and the main memory. (b)现在,让我们在L2缓存和主存储器之间添加另一级缓存,即L3缓存。 Consider the following: 考虑以下:

  • Miss penalty to L3 cache (hit time of L3 cache): 13 clock cycles L3缓存未命中的罚款(L3缓存的命中时间):13个时钟周期
  • Hit rate of L3 cache: 81% L3缓存的命中率:81%
  • Miss penalty to main memory: 37 clock cycles 未命中损失到主存储器:37个时钟周期
  • Other specifications remain as part (a) 其他规格保留为(a)部分

For the same 2000 instruction program (which has 37% data transfer instructions), calculate the CPI. 对于相同的2000指令程序(具有37%的数据传输指令),请计算CPI。

(m1: miss rate of L1, m2: miss rate of L2, m3: miss rate of L3)

AMAT = HitTime_L1 
         + m1*(HitTime_L2 + m2*MissPenalty_L2)
           + m2*(HitTime_L3 + m3*MissPenalty_L3)

Is this formula correct and where do I add the miss penalty to main memory in this formula? 该公式正确吗?在此公式中,我应在哪里向主内存添加未命中罚款? It should probably be added with the miss penalty of L3 but I am not sure. 它应该有可能与L3的命中损失增加,但我不知道。

(a) The AMAT calculation is correct if you notice that the MissPenalty_L2 parameter is what you called Miss penalty to main memory. (a)如果您注意到MissPenalty_L2参数是您所谓的主内存缺失惩罚,则AMAT计算是正确的。

The CPI is a bit more difficult. CPI有点困难。 First of all, let's assume that the CPU is not pipelined (sequential processor). 首先,让我们假设CPU没有流水线(顺序处理器)。

There are 1.37 memory accesses per instruction (one access to fetch the instruction and 0.37 due to data transfer instructions). 每条指令有1.37个存储器访问权限(一次访问可获取指令,而由于数据传输指令有0.37个存储器访问权限)。 The ideal case is that all memory acceses hit in the L1 cache. 理想的情况是L1缓存中的所有内存都已命中。 So, knowing that: 因此,知道:

CPI(ideal) = CPI(computation) + CPI(mem) = 
             CPI(computation) + Memory_Accesses_per_Instruction*HitTime_L1 =
             CPI(computation) + 1.37*HitTime_L1

With real memory, the average memory access time is AMAT, so: 对于实际内存,平均内存访问时间为AMAT,因此:

CPI(actual) = CPI(computation) + Memory_Accesses_per_Instruction*AMAT =
              CPI(ideal) + Memory_Accesses_per_Instruction*(AMAT - HitTime_L1) =
              CPI(ideal) + 1.37*(AMAT - HitTime_L1)

(b) Your AMAT calculation is wrong. (b)您的AMAT计算错误。 After a miss at L2, it follows a L3 access that can be a hit or a miss. 在L2错过之后,它会跟随L3访问,可能是一次命中或错过。 Try to finish the exercise yourself. 尝试自己完成练习。

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