[英]integer comparison doesn't work in if statement (vhdl)
What is the error in the following code? 以下代码中的错误是什么?
In the testbench x
is set to "00001111"
, yet the else branch is executed (in the simulation all of y
's bits are set to high impedance state, but y
should equal x
). 在测试平台中,
x
设置为"00001111"
,但是执行else分支(在仿真中, y
的所有位都设置为高阻抗状态,但是y
应该等于x
)。 I'm using XILNX ISE Design Suite
and ISim
as simulation environment. 我正在使用
XILNX ISE Design Suite
和ISim
作为仿真环境。 Thanks in advance. 提前致谢。
entity test is
Port ( x : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end test;
architecture Behavioral of test is
signal tmp : integer;
begin
process(x)
begin
tmp <= to_integer(unsigned(x(3 downto 0)));
if tmp = 15 then
y <= std_logic_vector(to_unsigned(tmp, 8));
else
y <= "ZZZZZZZZ";
end if;
end process;
end Behavioral;
The tmp
is a signal, thus it takes a delta delay before it reveals the value assigned by (pkg_sig_1'range) <= z(pkg_sig_1'range);
tmp
是一个信号,因此在显示(pkg_sig_1'range) <= z(pkg_sig_1'range);
分配的值之前要经过一个增量延迟(pkg_sig_1'range) <= z(pkg_sig_1'range);
. 。 So when the process is triggered at the change of
x
, the tmp
will have the previous value in the if tmp = 15 then ...
, and the new value of tmp
is not assigned until after the process is completed. 因此,当在
x
的变化处触发过程时, if tmp = 15 then ...
,则tmp
将具有先前的值,并且直到过程完成后才分配tmp
的新值。
Add tmp
to the sensitivity list, or change tmp
to a variable in the process, like: 将
tmp
添加到敏感度列表,或在此过程中将tmp
更改为变量,例如:
process(x)
variable tmp : integer;
begin
tmp := to_integer(unsigned(x(3 downto 0)));
if tmp = 15 then
y <= std_logic_vector(to_unsigned(tmp, 8));
else
y <= "ZZZZZZZZ";
end if;
end process;
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