Cortex-M4中的RAM存储器访问数量

Question

I using a Cortex-M4 in a STM32F4 board, developing in a Keil uVision5 and I am trying to count the exact number of reads and writes performed by the CPU in the memory RAM. Including loads, stores and fetched instructions. With the help of instruction set simulator I can calculate the number of load/stores and executed instructions, however I need to make sure that is a good approximation. I am aware of the DTW registers, but they don't have enough information.

Answer 1

Cortex-M4 has only the DWT registers which can provide some limited performance information. There is no equivalent to the PMU (performance monitor unit) which might provide the information you're looking for in a larger core. Still, you're more likely to see a count of executed instructions rather than fetches on the instruction interface.

You can use ETM trace to confirm the sequence that you see in simulation (if there are real-time events which might make simulation inaccurate), but this will only provide the same 'executed instruction' view.