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如何在Verilog中使用计数器显示数字序列

[英]How can I show a sequence of numbers using a counter in Verilog

For example a have to show 0 , 2 , 4 , 0 , 2 , 4 .. I use an output with 8 segments - less important . 例如,必须显示0、2、4、0、2、4 ..我使用具有8个细分的输出-不那么重要。

 output reg [7:0] data
 always @ (*) begin             
 case                                
 1:data= 8'b00000011; //number 0                        
 2:data= 8'b00100101; //number 2                     
 3:data= 8'b10011001; //number 4 
 default:data=8'b00000011;
 endcase
 end

And the counter : 和柜台:

input clock,
input reset,
output [7:0] out
reg [31:0] counter;
always @ (posedge clock) begin
if(reset==1)  counter <= 0;
else counter <= counter + 1;
end

My question is can I increment the case value instead of counter ? 我的问题是我可以增加大小写值而不是计数器吗? Like : 喜欢 :

always @ (posedge clock) begin
if(reset==1)  case <= 1;
else case <= case + 1;
if(case==3) reset<=1;
end

If not then how can I do this ? 如果没有,我该怎么办?

Your case statement is wrong. 您的案件陈述有误。 It should select based on the counter value: 它应基于计数器值进行选择:

always @ (*) begin             
 case(counter)
  1: data= 8'b00000011; //number 0                        
  2: data= 8'b00100101; //number 2                     
  3: data= 8'b10011001; //number 4 
  default:data=8'b00000011;
 endcase
 end

Your counter should be: 您的柜台应该是:

always @ (posedge clock) begin
  if(reset==1 || counter == 3)  counter <= 1;
  else counter <= counter + 1;
end

Note that case is a keyword. 请注意, case是关键字。 You can't use it in an expression. 您不能在表达式中使用它。

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