如何根据开关的值有条件地将参数传递给模块？ （verilog）

Question

does anyone know the correct method of passing a parameter to a verilog module conditionally? For example, I am doing a uart assignment, the uart itself can process 7 or 8 data bits per word. I basically need a way to pass 7 or 8 down to the uart module if the switch is high or low. I tried an always case statement but kept getting errors.

I know how to pass by name the parameter for example:

module top
#(parameter DATABITS = 7,
parameter DATABITS2 = 8)
(input [1:0] sw);

// Sorry I didnt list the whole code just tidbits to get the point across

...... rest of code here....... 

// My attempt at an always case statement. localparam dbit = 0;

always @(*)
begin 
        case(sw) 
            2'b00: begin
                dbit = DBIT1;
                end
            2'b01: begin
                dbit = DBIT2;
                end
        endcase
end // always @ (...)


UART #(.DATABITS(dbit)) UART_MODULE (.......ports etc in here); 

Answer 1

You use the module parameters to create modules that can be customized when you instantiate that module. However, once your netlist has been elaborated, the configuration of your UART_MODULE is fixed, based on the values you passed in as parameters.

The module cannot be "re-parameterized" during run-time. If you really do want to modify the data width on the fly you will have to add a 7/8-bit flag to your module's port list and add code to the module itself to handle the variable data width indicated by that flag.