CRC /奇偶校验/汉明保护16位并行总线

Question

I've got a Cortex-M4 based MCU linked to a FPGA via a 16-bit parallel memory bus interface. In essence the FPGA behaves like an external memory mapped to the memory space of the MCU: the MCU presents an address followed by either a data word (write) or reading the word presented by the FPGA (read).

I want to protect both read and write against transmission errors both during addressing and data write/read. However, I don't expect many bit errors since the distance between both parts is short.

I can easily implement checking and generating of either parity, hamming codes or CRC inside the FPGA. However, doing the same (checking and generating) in the uC seems comparatively harder since I don't want to cripple the throughput. Without error detection, reading and writing of 16-bit words takes around 4-6 processor cycles and is thus rather fast. Consequently I don't want to spend hundred of cycles on protective measures.

In the end I am looking for a moderately efficient error detection method for 16-bit data that is implemented in a uC in as few cycles as possible.

Answer 1

It's (in my experience) quite rare to protect a parallel bus like this. It's of course done in PC and server class hardware with ECC RAM and so on, but rarely in microcontrollers.

If your particular Cortex-M4 implementation has a hardware CRC block, you might be able to stream the data there, assuming you can simply add a word of CRC to the end of each bus transfer. That would probably still slow it down by at least a factor of 2-3 though, since each word coming to/from the FPGA must also be fed in software to the CRC unit.