C makefile和标头混淆

Question

I have a couple of general questions about Make files, headers, and including files in C, and am hoping to get an easy to interpret answer because all the tutorials go from "ok I understand this" to "what the heck is this" just in a couple lines. Lets say I have a program I want to create a makefile for.

**fileA.c** contains the main and calls functions in **fileB.c** and **fileC.c**

**fileB.c** contains getopts and stdlib but no other file or function from other file

(so normal headers, correct? nothing linking to any other file since it doesn't call anything. Or should it have fileA.c header since it is called from there?)

**fileC.c** contains functions that call header1.h (given header file for library)

I am just confused what headers are included and what I put in the make file to support make/clean functions. Since fileA.c calls functions from fileB.c and fileC.c do i create headers for them and #include them in fileA.c or do I write that into the makefile? If I include a header for something in the file and then create a makefile for the file, does it go to the pre-processor twice?

I think I may just be confused in the actual purpose of the makefile vs the header file, and that is causing me to lose my mind.

Thanks for taking the time to read and any help would be greatly appreciated.

edit:

for reference,

fileA.o: fileA.c fileA.h
${CC} ${CFLAGS} -c fileA.c

so, since fileA isn't called by anything this would be correct (I do pass address from fileA to both fileB and fileC)?

would fileB.o: contain fileB.c fileB.h and thats it? or would it have the other headers?

Answer 1

The first step for you, is to forget about the makefiles. Just setup your project in C, and to compile it, run the gcc commands by hand, or if you get tired of that, write them one after another in a shell script and run that.

Make sure it all runs to your satisfaction, before you attempt to write a Makefile .

You will probably have calls like

gcc -c fileB.c

and

gcc fileA.o fileB.o fileC.o -o fileA

The Makefile cannot be written if you are having trouble doing it "by hand", you understand?

Now, there comes the time to write the Makefile . To do that, you need "rules". A rule is something like this:

file_to_write:  all the files that impact file_to_write
    command to create the file to write

Each rule should describe how to create one file. That file is on the left of : . It is called a "target". On the right of : are listed the "prerequisites".

Listen carefully now. The prerequisites, are all the files, that, if changed, could result in the target behaving differently.

Below that, is the "recipe" - that is the command that reads the prerequisites and produces the target.

If the recipe reads some files, most likely those files must be in the prerequisite list.

So for example, you will have a rule to produce fileA like this:

fileA: fileA.o fileB.o fileC.o Makefile
    gcc fileA.o fileB.o fileC.o -o fileA

You see, if any file....o were different, fileA could be different too, that's why they are in the prerequisites. Also, you realize, that if Makefile itself were different, then fileA could end up different, because, the recipe could have changed.

In theory, if you changed the gcc file, for a newer revision for example, that could change the functionality of fileA as well. But typically we don't include tools files like gcc that change infrequently and are not under source control.

Of course, you will have another rule for fileA.o . This rule will probably have fileA.c and some headers that are read when fileA.c is compiled, as prerequisites. And so forth.

fileA.c does not need a rule. Why? Because it is not created by the build, it is always already there.

Answer 2

If fileA.c is dependent on fileB.c and fileC.c your makefile should be:

fileA: fileB.o fileC.o fileA.o
    $(CC) fileB.o fileC.o fileA.o -o fileA