Makefile 有两个.c 文件和没有 header

Question

Trying to write a makefile with two.c files and no header. However, it seems examples online have shown the makefile with a header.

So i tried to write a header file and it would tell me a function is redefined somewhere else. my header consisted of declarations of functions in both my.c files.

#ifndef HEADER_H 
#define HEADER_H 

void calc(void parameters); 
int main(int argc, char* argv[]); 

struct compArray
   { 
   int start; 
   int end; 
   int thr; 
   int m; 
   int r; 
   };

#endif

I'm positive that's not how you write a header but ideally I'd like to have my makefile without a header. Below is my Makefile:

all:    thr_atomic.o thr_reduce.o
gcc -o make thr_atomic.o thr_reduce.o -lm -pthread

thr_atomic.o: thr_atomic.c
gcc -c thr_atomic.c

thr_reduce.o: thr_reduce.c
gcc -c thr_reduce.c

Is it possible to create a makefile without a header? My two.c files are independent of each other. If so how do I go about doing that? And if not, what would I put in my header.h to tell the computer that my variables are not being redefined and are independent from each other?

Answer 1

You can use the following Makefile:

all: thr_atomic thr_reduce

thr_atomic: thr_atomic.c 
gcc thr_atomic.c -lm -pthread 

thr_reduce: thr_reduce.c 
gcc thr_reduce.c -lm -pthread <newline>

However, since it seems the two programs are totally independent, I would rather make two separate makefiles.

Answer 2

From what I can understand from your question, you don't need a header file in order to compile C code using a Makefile. Makefiles don't have anything to do with source code. All a Makefile does is run a command(s) if the file(s) you've specified have been updated.

# Makefile
outfile: infile1 infile2
    command1
    command2
    # ^ commands MUST begin with a tab

If you run make outfile , this is what happens:

1. If outfile does not exist, then make runs command1 , and then runs command2 .
2. If outfile exists, but infile1 and infile2 have not been updated since then, make will do nothing.
3. If outfile exists and infile1 or infile2 have been updated since outfile was last modified, then make will run command1 and then run command2 .

That's the basics of make and Makefiles. The files ( outfile , infile1 , infile2 etc.) and the commands ( command1 , command2 ) can be anything you like. There can also be any number of them present.

When it comes to compiling code, make is pretty useful because you can use it to recompile a binary file (also called an executable file) if the source files are changed, which is exactly what you want.

For example, this makefile creates a binary file (executable file) from two source files (and no header files):

# Makefile

# executable file is called "prog"
prog: a.o b.o
    gcc -o prog a.o b.o
    #   ^^^^^^^
    #    tell gcc to name the output file "prog"

# compile the first source file "a.c" to produce the object file "a.o"
a.o: a.c
    gcc -c a.c

# compile the second source file "b.c" to produce the object file "b.o"
b.o: b.c
    gcc -c b.c

If you do have header files, then you would need to change the compilation lines to this:

# Makefile

# ...

# compile a.c, which has an associated header file a.h 
a.o: a.c a.h
#        ^^^ add the header file here
    gcc -c a.c

If you are not clear about what header files are, then look them up somewhere or ask another question about them.