通用Makefile

Question

I am looking for a generic makefile, which will will build all C++ files in the current directory and all sub-directories (eg, source, test files, gtest, etc)

I have spent a few hours trying out several and finally settled on the solution from make file with source subdirectories .

I need to make three changes to it:

1. Gtest uses *.cc for its C++ files and I have others which use *.cpp
2. I need to be able to define multiple search paths.
3. Add compiler flags, like -W all

I have managed to break the makefile, shown below, such that running make gives me

make: *** No rule to make target %.cpp=%.o', needed by myProgram'. Stop.

How can I make it do those three things?

# Recursively get all *.cpp in this directory and any sub-directories
SRC = $(shell find . -name *.cc) $(shell find . -name *.cpp)

INCLUDE_PATHS = -I ../../../ -I gtest -I dummies

#This tells Make that somewhere below, you are going to convert all your source into 
#objects
# OBJ =  src/main.o src/folder1/func1.o src/folder1/func2.o src/folder2/func3.o

OBJ = $(SRC:%.cc=%.o %.cpp=%.o)

#Tells make your binary is called artifact_name_here and it should be in bin/
BIN = myProgram

# all is the target (you would run make all from the command line). 'all' is dependent
# on $(BIN)
all: $(BIN)

#$(BIN) is dependent on objects
$(BIN): $(OBJ)
    g++ 

#each object file is dependent on its source file, and whenever make needs to create
# an object file, to follow this rule:
%.o: %.cc
    g++ -c $(INCLUDE_PATHS) $< -o $@

---

[Update] Thanks for the help so far. To address a few of the comments, I have no control over the mixed *.cc and *.cpp fiel extensions, and I can say that there won't ever be a source file in the directory tree which I do not wish to include in the build.

I am still having trouble with the SRC, as no input files are found. I guess that I should look more into the find command as it has been a while since I used Linux.

Answer 1

Etan points out your problem. But you don't have to perform two replacements, just:

OBJ := $(addsuffix .o,$(basename $(SRCS)))

And, you should always be using := , not = , for assignment when using the shell function.

Answer 2

That is a rather poor makefile: it does not build header dependencies for you, so you are likely to end up with corrupted builds.

I shamelessly recommend this one .