GNU Makefile规则和依赖项

Question

I've been doing a lot of reading on how to write makefiles to build an application on Linux but I'm massively confused about the many different ways to apparently achieve the same goal.

This is what I have come up with so far to build an archive.

SHELL = /bin/sh

CXX = g++
DEBUG = -g
CXXFLAGS = -std=c++11 -Wall -pedantic #-Wextra
CPPFLAGS =  -I. \
            -I./include

SOURCES =   foo1.cpp \
            foo2.cpp \
            foo3.cpp

OBJECTS = $(SOURCES:.cpp=.o)

The following rule successfully compiles each source file into an object file and then creates an archive:

libfoo.a: $(OBJECTS)
    ar rvcs $@ $(OBJECTS)

%.o: src/%.cpp ./include/%.h
    $(CXX) -c $(CPPFLAGS) $(CXXFLAGS) -o $@ $< 

This also does the same thing:

libfoo.a: $(OBJECTS)
    ar rvcs $@ $(OBJECTS)

$(OBJECTS) : %.o:src/%.cpp
    $(CXX) -c $(CPPFLAGS) $(CXXFLAGS) -o $@ $< 

However, this fails with an error that there is no rule to make target 'foo1.o:%.h

libfoo.a: $(OBJECTS)
    ar rvcs $@ $(OBJECTS)

$(OBJECTS) : %.o:src/%.cpp %.o:%.h
    $(CXX) -c $(CPPFLAGS) $(CXXFLAGS) -o $@ $< 

Can someone please explain why it doesn't work and which approach is best?

The first option lists the header files as dependencies but the second option doesn't. That is my motivation for the third option.

How do I list the headers as dependencies using options 2 or 3?

TIA

Answer 1

The feature you're using in try #2 and try #3 is static pattern rules and the syntax looks like this:

<targets...> : <target-pattern> : <prerequisites...>

There can only be two colons, not three. You should write your try #3 above as:

$(OBJECTS) : %.o : src/%.cpp %.h
        $(CXX) -c $(CPPFLAGS) $(CXXFLAGS) -o $@ $< 

Note one critical thing: this rule will FAIL if you ever create any .cpp file which does not have an associated .h file. Just sayin'.