将x86_64程序集移植到AArch64

Question

I'm trying to convert some existing inline x86_64 assembly to AArch64 compatible version. I am encountering the following errors upon compilation:

/tmp/ccSvqF1I.s:72547: Error: operand 1 should be an integer register -- `str [0x4,x1],#0x43e00000'
/tmp/ccSvqF1I.s:72548: Error: operand 1 should be an integer register -- `str [20,x1],2'

The x86_64 code below if the original and the AARch64 code is my attempt at porting it.

x86_64 Assembly:

                __asm__(
                        "incq (%0)\n\t"
                        "jno  0f\n\t"
                        "movl $0x0, (%0)\n\t"
                        "movl $0x43e00000, 0x4(%0)\n\t"
                        "movb %1, %c2(%0)\n"
                        "0:"
                        :
                        : "r"(&op1->value),
                          "n"(IS_DOUBLE),
                          "n"(ZVAL_OFFSETOF_TYPE)
                        : "cc");

AArch64 Assembly

                __asm__(
                        "add %0, %0, #1\n\t"
                        "bvc  0f\n\t"
                        "mov %0, #0x0\n\t"
                        "str [0x4, %0], #0x43e00000\n\t"
                        "str [%c2, %0], %1\n\t"
                        "0:"
                        :
                        : "r"(&op1->value),
                          "n"(IS_DOUBLE),
                          "n"(ZVAL_OFFSETOF_TYPE)
                        : "cc");

Edit:Updated with new attempt and error messages

Answer 1

When you want to do something can not be describe by one instruction, you need to split it into several instructions.

The problem is that AArch64 doesn't have an instruction to store immediate value to a memory. You need to move immediate value to an register and then store the register to memory like:

movz    w2, #0x43e0, lsl #16         // move #0x43e00000 to a register
str w2, [x1, #20]                    // store to address [x1, #20]
orr w2, wzr, #0x2                    // move #0x2 to a register
str w2, [x1, #4]                     // store to address [x1, #4]

ARM instructions are RISC (Reduced instruction set computer) like instructions. The benefit is that instructions are all very simple and fixed length. X86 has more complicated instructions. But you still need to split your behaviour into several instructions if it hasn't an instruction support your behavour. You can find more information about AArch64 in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488d/CIHGGBGB.html .

Answer 2

A better solution might be to use the ldr= pseudo-op which would make the cryptic movz usage easier to read:

ldr  w2, =0x43e00000
str  w2, [x1, #20]

.. and so on. Your assembler should be smart enough to realize that it can use movz or some other instruction to generate the immediate in w2 , but in the worst case this'll come out as a literal pool load. While learning, ldr= is a boon, and you shouldn't try and game the assembler until you know it's broken or not as efficient as you.

Answer 3

Unfortunately, almost none of your assembly is correct. The A64 instruction set uses a load/store architecture. This means that there are specific instruction that load and store values from memory into and from registers. No other instructions access memory. So for example an ADD instruction can't access memory. This means that your add %0, %0, #1 statement doesn't increment op1->value , it increments the register that holds the address of op1->value . It's basically like you did op1++ in C instead of op1->value++ .

    zend_long temp;
    static zend_long const overflow = 0x43e0000000000000;
    asm("ldr %[temp], %[value]\n\t"
        "adds %[temp], %[temp], #1\n\t"
        "str %[temp], %[value]\n\t"
        "b.vc 0f\n\t"
        "mov %[temp], #%[overflow]\n\t"
        "str %[temp], %[value]\n\t"
        "mov %w[temp], #%[is_double]\n\t"
        "str %w[temp], %[type_info]\n\t"
        "0:\n\t"
        :
        [temp] "=&r" (temp),
        [value] "+m" (op1->value.lval),
        [type_info] "=m" (op1->u1.type_info)
        :
        [overflow] "N" (overflow),
        [is_double] "M" (IS_DOUBLE)
        : "cc");

You'll notice that the x86 INC instruction becomes three separate instructions. The first ones loads the value into a register, the second adds one to the register, and finally the the third stores it back.

The two constants 0x43e000000000000 and IS_DOUBLE happen to be ones that can be loaded into a register with a single instruction. Using the MOV pseudo instruction allows allows the assembler to figure out which one. Otherwise instead the LDR= pseudo instruction would have to be used to load the constant from memory. Either way, as claymore said in his answer you can't store an immediate value directly to memory.

Finally the asm statement uses the ADDS instruction instead of the ADD instruction. The former sets the condition flags according the result, the later doesn't. This whole point of the asm statement. It supposed to make signed overflow detection more efficient by checking the condition flags.