Makefile覆盖默认隐式规则

Question

Why this rule cannot override the default implicit rule ?

When make is invoked like: make myapp (suppose myapp.c is there). The make runs the default command to build and link the program instead the commands defined in this implicit rule:

#... omitted code
LCUS=$(LIBS)/libcus.a

#... omitted code
% : %.o $(LCUS)
        echo  !!! Custom build !!!
        $(MY_CMD) $< -o $@ $(LCUS)

Answer 1

Taken from the GNU online make manual :

You can override a built-in implicit rule (or one you have defined yourself) by defining a new pattern rule with the same target and prerequisites, but different commands.

So I would assume it is because the prerequisites are not the same as the implicit rule.

Also take from the make manual:

Linking a single object file n is made automatically from no by running the linker (usually called ld ) via the C compiler. The precise command used is $(CC) $(LDFLAGS) no $(LOADLIBES) $(LDLIBS) . This rule does the right thing for a simple program with only one source file. It will also do the right thing if there are multiple object files (presumably coming from various other source files), one of which has a name matching that of the executable file. Thus,

  x: yo zo 

when xc , yc and zc all exist will execute:

 cc -c xc -o xo cc -c yc -o yo cc -c zc -o zo cc xo yo zo -ox rm -f xo rm -f yo rm -f zo 

So basically make understands implicit rules for program files that are generated from .o files but when you throw in your static library it doesn't understand. A simple way to test would be to remove $(LCUS) from your dependencies (as a temporary measure) to see if it then uses your rule instead of the built in one. If it does then you know that is your problem. If simply adding myapp in replace of % is a problem because you want the rule to build multiple targets you can try the following:

$(APPS): % : %.o $(LCUS)

where $(APPS) is a variable containing all the applications you wish to build. This will allow one rule to build multiple targets. You could also skip the use of the variable altogether and place a space separated list. This is an example of a static pattern rule, more information can be found here . The difference between static pattern and implicit rules can be found here.

Answer 2

Your rule isn't the same as the built-in implicit rule so it doesn't cancel it.

Additionally, make always prefers a rule that doesn't require intermediate files to be built to one that does. If you pre-create the .a file make might use your rule instead (but it might not even still).

If you cancel the built-in rule and leave your rule in place it should work correctly I believe.