在Systemverilog中使用宏创建结构数组

Question

I've created a module with (example) two in and two out-puts. The definition of every in and output is delcared through a macro.

Is it possible to create it a bit more elegant (later usability)? Something like an array of inputs and outputs (NAME(i), in(i), out(i))?

It would be helpful, because i am later using much more out and inputs and there is a possbility using later loops to access the in/outputs much more elegant.

top:

`include "macro.sv"

module top (in_0, in_1, out_0, out_1);

    `STRUCT_i(in_0_temp,  10);
    `STRUCT_i(in_1_temp,  22);
    `STRUCT_i(out_0_temp,  55);
    `STRUCT_i(out_1_temp,  99);

    input   `STRUCT(in_0_temp)      in_0;
    input   `STRUCT(in_1_temp)      in_1;
    output  `STRUCT(out_0_temp)     out_0;
    output  `STRUCT(out_1_temp)     out_1;

...

    endmodule

Macro.sv :

`define STRUCT(NAME) \
struct_i_``NAME``

`define STRUCT_i(NAME, DATA) \
typedef struct packed { \
  logic [DATA:0]            info; \
  logic                     test1; \
  logic                     test2; \
    } `STRUCT(NAME)

Answer 1

There is no way to do this with an array because, by definition, an array is a collection of uniformly typed variables. Access with a dynamic index value requires that each element have an identical layout. It would not work even with simple bit vectors of different lengths. Your only synthesizable option is to declare info with a max size and hope the unused bits are optimized away.