[英]How to define a variable and then compile in a target [Makefile]
Having a Makefile i just want to adjust a variable and then compile, if i call a specific target. 有一个Makefile我只想调整一个变量,然后编译(如果我调用一个特定的目标)。 I have a working solution, how ever, it is not a nice one.
我有一个可行的解决方案,但是,它不是一个很好的解决方案。
How i compile: 我如何编译:
make
How i want to change a variable: 我要如何更改变量:
make debug
What needs to happen (how it works somehow): 需要发生什么(它如何工作):
debug:
@make TAG=debug
I basically call make in a make process, which does the work, but doesn't seem to be correct either. 我基本上在制作过程中调用make,该工作可以完成工作,但似乎也不正确。 I am looking for something like:
我正在寻找类似的东西:
debug:
TAG=debug
jump to first line and do the job
TAG=release
build:
@echo $(TAG)
debug: TAG=debug
debug: build
release: build
Usage: 用法:
> make
release
> make release
release
> make debug
debug
Update: Using TAG
in build prerequesites: 更新:在构建先决条件中使用
TAG
:
TAG=release
pre:
@echo pre build $(TAG)
build: pre
@echo $(TAG)
debug: TAG=debug
debug: build
release: build
Output: 输出:
~/workspace (master) $ make build
pre release
release
~/workspace (master) $ make debug
pre debug
debug
~/workspace (master) $ make release
pre release
release
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