How to define a variable and then compile in a target [Makefile]

Question

Having a Makefile i just want to adjust a variable and then compile, if i call a specific target. I have a working solution, how ever, it is not a nice one.

How i compile:

make

How i want to change a variable:

make debug

What needs to happen (how it works somehow):

debug:
    @make TAG=debug

I basically call make in a make process, which does the work, but doesn't seem to be correct either. I am looking for something like:

debug:
    TAG=debug
    jump to first line and do the job

Answer 1

TAG=release

build:
    @echo $(TAG)

debug: TAG=debug
debug: build

release: build

Usage:

> make
release
> make release
release
> make debug
debug

Update: Using TAG in build prerequesites:

TAG=release

pre:
    @echo pre build $(TAG)

build: pre
    @echo $(TAG)

debug: TAG=debug
debug: build

release: build

Output:

~/workspace (master) $ make build
pre release
release
~/workspace (master) $ make debug
pre debug
debug
~/workspace (master) $ make release
pre release
release