[英]VHDL - library doesn't work
I've create a new project on Quartus II with VHDL, but after I run it give me the errors shown below. 我已经在带有VHDL的Quartus II上创建了一个新项目,但是在运行它后,出现以下错误。 Do you have any idea why?
你知道为什么吗?
Error (10481): VHDL Use Clause error at test_VHDL.vhd(5): design library "work" does not contain primary unit "std_arith"
错误(10481):test_VHDL.vhd(5)上的VHDL使用子句错误:设计库“工作”不包含主单元“ std_arith”
Error (10800): VHDL error at test_VHDL.vhd(5): selected name in use clause is not an expanded name
错误(10800):test_VHDL.vhd(5)处的VHDL错误:use子句中的选定名称不是扩展名称
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful.
错误:Quartus II 64位分析和综合未成功。 2 errors, 1 warning
2个错误,1个警告
Error: Peak virtual memory: 1003 megabytes错误:虚拟内存峰值:1003兆字节
Error: Processing ended: Sat Dec 5 19:50:39 2015错误:处理结束:2015年12月5日星期六19:50:39
Error: Elapsed time: 00:00:13错误:经过时间:00:00:13
Error: Total CPU time (on all processors): 00:00:38错误:CPU总时间(在所有处理器上):00:00:38
Error (293001): Quartus II Full Compilation was unsuccessful.错误(293001):Quartus II完全编译失败。 4 errors, 1 warning
4个错误,1个警告
Here is my code: 这是我的代码:
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.std_arith.all; --extinde operatorul ” + “ la opera]ii \ntre semnale
--[i numere \ntregi
entity SUM is
port (a : in std_logic_vector(3 downto 0);
b : in std_logic;
ini,start,clk,a_disponibil,b_disponibil : in std_logic;
sum : out std_logic_vector(4 downto 0);
q : inout std_logic_vector(4 downto 0));
end SUM;
architecture arch_SUM of SUM is
signal load_a,load_b,reset,load_s : std_logic;
signal z : std_logic_vector(0 to 3);
type STARE is (S0,S1,S2,S3,S4); --st`rile automatului
signal S : STARE;
begin
--NUMARATOR
---------------------------------------------------------------
NUM : process(b)
begin
if rising_edge(b) then
if reset='1' then q<=(others=>'0');
elsif load_a='1' then
for i in 3 downto 0 loop --\ncarc` operandul a
q(i) <= a(i); --\n ultimii 3 bistabili
end loop; --ai num`r`torului
elsif load_b='1' then
q <= q+1; --adun` b la a
end if;
end if;
end process NUM;
--REGISTRU
--------------------------------------------------------------------
REG: process(clk)
begin
if rising_edge(clk) then
if reset='1' then sum<=(others=>'0');
elsif load_s='1' then
sum<=q;
end if;
end if;
end process REG;
--AUTOMAT
-----------------------------------------------------------------------------------
AUTOMAT : process(ini,clk)
begin
if INI='1' then s<=S0; --ini]ializeaz` automatul
elsif rising_edge(clk) then
case S is --descrie diagrama st`rilor
when S0 =>
if start='1' then S<=S1;
else S<=S0;
end if;
when S1 =>
if a_disponibil='1' then S<=S2;
else S<=S1;
end if;
when S2 =>
if b_disponibil='1' then S<=S3;
else S<=S2;
end if;
when S3 =>
if b_disponibil='0' then S<=S4;
else S<=S3;
end if;
when S4 => S<=S0;
end case;
end if;
end process AUTOMAT;
with S select
z<= "0000" when S0, --genereaz` ie[irea
"0010" when S1,
"1000" when S2,
"0100" when S3,
"0001" when others;
load_a <= z(0);
load_b <= z(1); --conexiuni interne
reset <= z(2);
load_s <= z(3);
end arch_SUM;
Have anyone idea why and how can solve it? 有谁知道为什么以及如何解决呢?
The statement use work.std_arith.all;
该语句
use work.std_arith.all;
introduces the sysnthesis compiler to look for a package std_arith
in the same library as of the VHDL file. 引入了sysnthesis编译器,以在与VHDL文件相同的库中查找包
std_arith
。 If you didn't specify one in the Quartus project settings, that it will be the default library. 如果您未在Quartus项目设置中指定一个,它将成为默认库。 In this case, you have to provide your own implementation of the package and to add this file to the Quartus project as well.
在这种情况下,您必须提供自己的软件包实现,并将此文件也添加到Quartus项目中。
If you are looking for the non-standard package from Synopsys, then you must change the line to use ieee.std_logic_arith.all;
如果要从Synopsys寻找非标准软件包,则必须更改该行以
use ieee.std_logic_arith.all;
. 。 But, this library does not define an operator
+
for the type std_logic_vector
. 但是,此库未为
std_logic_vector
类型定义运算符+
。 EDIT The required operator is defined in the package std_logic_unsigned
, if you want to treat your std_logic_vector
s as unsigned numbers. 编辑如果要将
std_logic_vector
视为无符号数字,则在包std_logic_unsigned
定义了所需的运算符。 The package is included with use ieee.std_logic_unsigned.all;
该软件包包含在
use ieee.std_logic_unsigned.all;
. 。 If you want signed arithmetic instead, then include
use ieee.std_logic_signed.all;
如果要使用带符号算术,则请
use ieee.std_logic_signed.all;
. 。
But, I recommend to use the standard IEEE library ieee.numeric_std
instead, which defines arithmetic operators on the vector-types unsigned
and signed
. 但是,我建议改为使用标准IEEE库
ieee.numeric_std
,该库在unsigned
和signed
的向量类型上定义算术运算符。
For example, declare in the entity 例如,在实体中声明
sum : out unsigned(4 downto 0);
q : inout unsigned(4 downto 0);
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