myhdl约束将多个引脚关联到一个变量

Question

I will be using an iCE40HX8K

given the evaluation boards constraint file

set_io LED3 A2  
set_io LED7 B3  
...  
etc  

whats the best way to bundle all 8 LED's into one variable I had trouble associating things with my constraint file and ended up with something like this

#main module
def ledcount(LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8, clk):

when writing a register to the LED's I'm having to resort to this

op.next = op + 1
LED1 = op[0]
...
LED8 = op[7] 

I'm generating verilog like this... (I did have single sliced bits from a single signal here but it seemed to cause problems - ie LED3 in constrains not assigning to anything)

clock = Signal(bool(0))
l1 = Signal(bool(0))
...
l8 = Signal(bool(0))
toVerilog(ledcount, l1, l2, l3, l4, l5, l6, l7, l8, clock)

bad enough but its going to become unwieldy with a parallel address and data bus ...

I notice in the generated verilog LED1-8 are specified like this

input LED1;
...
input LED8;

before the always clause and inside the always

reg LED1;
...
reg LED8;

While all this compiles (Hardware should arrive tomorrow!) and it might(?) even work... I'm sure it can be done better!

I'd be quite happy handling the LED's together as a single byte using bit manipulation...

Answer 1

The most straight forward is to change your constraints to

set_io LED[2] A2

and then use a single LED port

def ledcount(leds, clk)

and it can be converted to

clk = Signal(bool(0))
leds = Signal(intbv(0)[8:])
myhdl.toVerilog(ledcount, leds, clk)