[英]Passing a signal name into a verilog task
Instead of this task just toggling tb.stimulus.top.Ichip0.vbiash high and low ten times I would like to be able to call it passing in any signal tb.stimulus.top.Ichip0.vbiasl, tb.stimulus.top.Ichip0.vbiasx, or tb.stimulus.top.Ichip0.vbiasz and make them toggle as well. 代替此任务,只是将tb.stimulus.top.Ichip0.vbiash高低切换十次,我希望能够将其传递给任何信号tb.stimulus.top.Ichip0.vbiasl,tb.stimulus.top.Ichip0 .vbiasx或tb.stimulus.top.Ichip0.vbiasz并使它们切换。 For example toggle_signal(tb.stimulus.top.Ichip0.vbiasl); 例如toggle_signal(tb.stimulus.top.Ichip0.vbiasl); Is it possible to do this. 是否有可能做到这一点。 If so I would really appreciate an example of how I would accomplish this. 如果是这样,我将非常感谢我如何实现此目标的示例。
task toggle_signal;
begin
for (monpad_index=0; monpad_index < 10; monpad_index = monpad_index + 1)
begin
#1000;
force tb.stimulus.top.Ichip0.vbiash = 1'b1;
#1000;
force tb.stimulus.top.Ichip0.vbiash = 1'b1;
#1000;
end
end
You cannot pas the name of a single to a task. 您不能将单个名称命名为任务。 But you can create a macro to do this. 但是您可以创建一个宏来执行此操作。
`define toggle_signal(sig) \
for (monpad_index=0; monpad_index < 10; monpad_index = monpad_index + 1) \
begin \
#1000 force tb.stimulus.top.Ichip0.sig = 1'b1; \
#1000 force tb.stimulus.top.Ichip0.sig = 1'b0; \
#1000; \
end
and then write 然后写
`toggle_signal(vbiash)
`toggle_signal(vbiasl)
If you are not afraid do dive into a little C programming, you could write your own PLI/VPI. 如果您不害怕深入一点C编程,则可以编写自己的PLI / VPI。 I suggest checking out IEEE Std 1800-2012 's sections on PLI/VPI (§ 36, 37, & 38). 我建议查看有关PLI / VPI的IEEE Std 1800-2012的部分(第36、37和38节)。 Your come may looks something like the following (Note, the code is a starting reference. I haven't tested it): 您的到来可能看起来像以下内容(请注意,代码是一个开始参考。我尚未测试过):
static int my_vpi_force_release_calltf(PLI_BYTE* user_data) {
vpiHandle sys, argv, signal;
p_vpi_value p_value;
int force_release;
force_release = (int) user_data;
sys = vpi_handle(vpiSysTfCall, 0);
argv = vpi_iterate(vipArgument, sys);
signal = vpi_handle_by_name(vpi_get_str(vpi_scan(argv), 0);
if (force_release != 0 ) {
vpi_get_value(vpi_scan(argv), p_value);
vpi_put_value(signal, p_value, 0, vpiForceFlag);
} else {
vpi_get_value(signal, p_value);
vpi_put_value(signal, p_value, 0, vpiReleaseFlag);
}
return 0;
}
void register_my_vpi_force_release()
{
s_vpi_systf_data data;
data.type = vpiSysTask;
data.calltf = my_vpi_force_release_calltf;
data.tfname = "$my_force";
data.user_data = (PLI_BYTE8 *) 1;
vpi_register_systf(&data);
data.tfname = "$my_release";
data.user_data = (PLI_BYTE8 *) 0;
vpi_register_systf(&data);
}
You can call your PLI/VPI tasks in verilog: 您可以在verilog中调用您的PLI / VPI任务:
task toggle_signal( input [80*8-1:0] path_str );
integer index;
begin
for (index=0; index < 10; index = index + 1)
begin
#1000;
$my_force( path_str, 1'b1);
#1000;
$my_force( path_str, 1'b0 );
#1000;
end
$my_release( path_str );
end
endtask
...
initial begin
...
toggle_signal( "tb.stimulus.top.Ichip0.vbiash" );
...
end
If you don't want to write your own custom PLI/VPI, then I suggest enabling SystemVerilog and include UVM (the major simulators have UVM build in, or download it yourself). 如果您不想编写自己的自定义PLI / VPI,则建议启用SystemVerilog并包含UVM (主要的模拟器已内置UVM或自行下载)。 The UVM library has a build in method uvm_hdl_force
/ uvm_hdl_release
. UVM库具有内置方法uvm_hdl_force
/ uvm_hdl_release
。
Here you go. 干得好。 The following code passes a signal name as a parameter to a task then prints the signal name as a string. 以下代码将信号名称作为参数传递给任务,然后将信号名称打印为字符串。 Tested in iverilog
. iverilog
测试。
reg this_is_some_signal_name;
`define NAME(net) `"net`"
task print;
input reg [32*8] str;
begin
$display(">>> %0s", str);
end
endtask
initial begin
print(`NAME(this_is_some_signal_name));
$finish;
end
Outputs: 输出:
>>> this_is_some_signal_name
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