如何从Verilog的可变长度输入信号中得出固定长度输出信号

Question

I have an HDL Block in which the output follows the input in such a way that when input signal is binary 0, output remains 0 but when input turns 1, output turns 1 for a preset number of clock cycles (signal_length). ie input may remain high for suppose 65 or 66 clock cycles but output should remain high for preset number of clock cycles. I tried to accomplish the task with Verilog. But I am having an error and I don't know how to rectify. Hope someone can help.

module last_ind
#(
parameter MAX_LENGTH = 262144,
parameter signal_length
)
(
   input           clk,      
   input [17:0] pkt_length,
   input           tdata,
   output          tlast
);
reg [17:0] cnt = 0;

always @ (posedge clk)
begin
if ((tdata==1) && (cnt<signal_length)) 
        tlast <= 1;
 else
        cnt <= 0;
 end
 assign   cnt <= cnt + 1'b1;
 endmodule

Answer 1

maybe something like this will do. It should keep the signal up for the signal_length cycles and will reset when tdata gets '0'. You decide on the correct protocol though.

 reg [17:0]      cnt = signal_length;

 always @ (posedge clk) begin
    if (cnt < signal_lenth)
      cnt <= cnt + 1;
    else if (cnt == signal_length + 1 && tdata == 1 && tlast == 0) begin
      cnt <= 0;
      tlast <= 1;
    end
    else if (tdata == 0) begin 
       cnt <= sighal_length + 1;
       tlast <= 0;
    end
    else
       tlast <= 0;
end