[英]Isim is not testing all bits in test fixture
I am trying to test all possible cases of inputs for my Verilog code.我正在尝试为我的 Verilog 代码测试所有可能的输入情况。 I set it up with for loops.我用 for 循环设置它。
for(sel = 0;sel < 4;sel=sel+1) begin
for(a = 0;a < 8;a=a+1) begin
for(b = 0;b < 8;b=b+1) begin
#50;
end
end
end
It was working earlier, but I must have changed something or Isim might have a bug.它更早工作,但我必须更改某些内容,否则 Isim 可能有错误。 I initialized a, b and sel, too.我也初始化了 a、b 和 sel。
reg [2:0] a;
reg [2:0] b;
reg [1:0] sel;
When I try to simulate the tb file, it only loops through b repeatedly!当我尝试模拟 tb 文件时,它只会重复循环 b! Why could this be?为什么会这样?
Also, when I change b bounds to <7, it will begin to loop through a, but I have to change a bounds to <7 to loop through sel.此外,当我将 b 边界更改为 <7 时,它将开始循环遍历 a,但我必须将 a 边界更改为 <7 以循环遍历 sel。 Although this partially works, it skips the cases of 111 for a and b and 11 for sel.虽然这部分有效,但它跳过了 a 和 b 的 111 和 sel 的 11 的情况。
Furthermore, I decided to test the bits manually for all cases, and it's showing the correct result.此外,我决定在所有情况下手动测试这些位,它显示了正确的结果。
You have an infinite loop because your end condition ( b < 8
) is always true.您有一个无限循环,因为您的结束条件 ( b < 8
) 始终为真。 You can easily prove this to yourself with the following code.您可以使用以下代码轻松地向自己证明这一点。 You can see 0-7 repeating many times:你可以看到 0-7 重复了很多次:
module tb;
reg [2:0] b;
initial begin
for (b = 0;b < 8;b=b+1) begin
$display(b);
#50;
end
end
initial #1000 $finish;
endmodule
Output:输出:
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
Since you declared b
as a 3-bit signal, it's range of values is 0 through 7. Therefore, b is always less than 8. When b=7, b+1=0, not 8.由于您将b
声明为 3 位信号,因此它的值范围是 0 到 7。因此,b 始终小于 8。当 b=7 时,b+1=0,而不是 8。
Changing 8 to 7 displays only 0-6 once because the end condition ( b < 7
) becomes false.将 8 更改为 7 仅显示 0-6 一次,因为结束条件 ( b < 7
) 变为假。
Here is one way to loop from 0 to 7 once:这是从 0 到 7 循环一次的一种方法:
module tb;
reg [2:0] b;
initial begin
b = 0;
repeat (8) begin
$display(b);
#50;
b=b+1;
end
end
endmodule
Another common way is to declare b
as an integer
instead of a 3-bit reg
.另一种常用方法是将b
声明为integer
而不是 3 位reg
。 Then for (b = 0;b < 8;b=b+1) begin
loops 0-7 once because b can increase to 8. An integer
is a 32-bit signed value (refer to IEEE Std 1800-2012, section 6.11 Integer data types).然后for (b = 0;b < 8;b=b+1) begin
循环 0-7 一次,因为 b 可以增加到 8。 integer
是 32 位有符号值(请参阅 IEEE Std 1800-2012,第 6.11 节整数数据类型)。
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