结构性Verilog计数器初始化

Question

So I'm a newcomer to verilog and am trying to make a counter using structural verilog. The counter is made of 4 D-type flip flops.
The functionality of the flip flops has been verified so that's not the problem.

The problem I'm finding is that when beginning the simulation, the wire l1 (linking d to q_bar) is undefined.
This can be solved by resetting the flip flop and giving q_bar a defined value.
However, when it comes to FF1, the reset does not work since it is a synchronous reset and there is no rising clock edge when the reset is high.

So my question is,

How can I reset the flip-flops, or even better is there any way of initializing the output of the flip flop?

This is my code:

module sr_latch(q, q_bar, r, s);
   output q;
   output q_bar;
   input  s;
   input  r;

   nor #1(q_bar, s, q);
   nor #1(q, r, q_bar);
endmodule 


module d_latch(clk,q,q_bar,d);
  output q, q_bar;
  input clk,d;
  wire d_bar,r,s;

  sr_latch A(q, q_bar, r, s);

  not (d_bar, d);
  and (s, d, clk);
  and (r, d_bar, clk);

endmodule


module d_type_ff (clk, d, q, q_bar);
  output q, q_bar;
  input clk, d;
  wire d1, d2, clk_bar;

  d_latch Master(clk_bar, d1, d2, d);
  d_latch Slave(clk, q, q_bar, d1);

  not(clk_bar, clk);

endmodule

module d_type_ff_rst (clk, d, q, q_bar, reset);
    output q;
    output q_bar;
    input clk, d, reset;
    wire d_in, rst_bar;

    d_type_ff A(clk, d_in, q, q_bar);

    not(rst_bar, reset);
    and(d_in, rst_bar, d);

endmodule

module counter_S (clk, reset, enable, count);
  input clk, reset, enable;
  output  [3:0] count;       //MSB count[3]
                            //LSB count[0]
  wire l1, l2, l3, l4;

  d_type_ff_rst FF0 (clk, l1, count[0], l1, reset);
  d_type_ff_rst FF1 (l1, l2, count[1], l2, reset);
  d_type_ff_rst FF2 (l2, l3, count[2], l3, reset);
  d_type_ff_rst FF3 (l3, l4, count[3], l4, reset);


endmodule

And the testbench

module counter_tm();
wire [3:0] count;
reg clk, reset, enable;


counter_S DUT(clk, reset, enable, count);

 always #10 clk <= ~clk;


initial
begin

  clk <= 1'b0;
  reset = 1'b1;
  enable = 1'b1;

  #10
  reset = 1'b0;


end
endmodule

Answer 1

You change reset coincident with the edge of the clock. You need to hold reset active a little longer.