[英]Verilog always inside a generate block is throwing error
I am trying to execute addition through using ripple carry adder using for loop and I wanted the operation to be performed only at posedge of clock. 我试图通过使用带有for循环的纹波进位加法器执行加法运算,我希望仅在时钟的posege上执行该操作。 For doing so, I have used a generate block and used for loop inside the generate block.
为此,我使用了一个generate块,并将其用于generate块内的循环。 If I use without always statement it would work fine, but when I add the always block it would result in error when simulating.
如果我不使用always语句,则可以正常工作,但是在添加always块时,在模拟时会导致错误。 Below is the code:
下面是代码:
genvar i;
generate
always @(posedge clk)
for(i=0;i<=31;i=i+1) begin : generate_block
fulladd f1(.sum(sum[i]),.cin(cout1[i]),.a(b[i]),.b(temp[i]),.cout(cout1[i+1]));
end
end
endgenerate
Here fulladd is a different module. 这里fulladd是一个不同的模块。
Below is the error that I am getting when simulating: 以下是我在模拟时遇到的错误:
Error-[IBLHS-CONST] Illegal behavioral left hand side
add32.v, 36
Constant Expression cannot be used on the left hand side of this assignment
The offending expression is : i
Source info: i = 0;
Error-[IBLHS-CONST] Illegal behavioral left hand side
add32.v, 36
Constant Expression cannot be used on the left hand side of this assignment
The offending expression is : i
Source info: i = (i + 1);
Error-[SE] Syntax error
Following verilog source has syntax error :
"add32.v", 37: token is '('
fulladd
f1(.sum(sum[i]),.cin(cout1[i]),.a(b[i]),.b(temp[i]),.cout(cout1[i+1]));
add32.v is the design module name. add32.v是设计模块名称。 I have used synopsis vcs.
我已经使用过概要vcs。 I am new to verilog programming, please explain the underlying concept which I have mistaken.
我是Verilog编程的新手,请解释一下我错误的基本概念。 Thanks in advance
提前致谢
Addition logic & registering signals should be treated separately. 加法逻辑和注册信号应分开处理。 Pull the relevant input & output signals from adder and register them separately at posedge.
从加法器中提取相关的输入和输出信号,并分别在posege处进行注册。
see this CLA adder implementation code for reference 请参阅此CLA加法器实现代码以供参考
I have implemented a generic ripple carry adder as below. 我已经实现了一个通用的纹波进位加法器,如下所示。
// ripple_carry_adder.v
// NOTE : I have registered the outputs only. Inputs are asynchronous.
`timescale 1ns / 10 ps
module ripple_carry_adder
#( parameter COUNT = 32 // width of RCA port
)
(
input clk,rst,
input Carry_in,
input [COUNT-1:0] A, B,
output reg [COUNT-1:0] Sum,
output Carry_out
);
reg [COUNT-1:0] Carry,Cout;
assign Carry_out = Cout[COUNT-1];
always@(posedge clk or posedge rst)
begin
if (rst)
begin
Carry = 'b0;
Sum = 'b0;
Cout = 'b0;
end
else
begin
Cout = ((A & B) | ((A ^ B) & Carry));
Sum = (A ^ B ^ Carry);
Carry = {Cout[COUNT-1:1],Carry_in};
end
end
endmodule
I don't see why you need an always block in this case. 我不明白为什么在这种情况下您需要始终阻止。 You would never instantiate anything at the posedge of a clock.
您永远不会在时钟的姿势上实例化任何东西。
The way I go about writing generate blocks is to first figure out what one instance (without the generate) would look like: 我编写generate块的方式是首先弄清楚一个实例(不包含generate)是什么样的:
fulladd f1(.sum(sum[0]),.cin(cout1[0]),.a(b[0]),.b(temp[0]),.cout(cout1[1]));
Then, to scale this to instantiate multiple instances of fulladd: 然后,进行缩放以实例化fulladd的多个实例:
genvar i;
generate
for(i=0;i<=31;i=i+1) begin : generate_block
fulladd f1(.sum(sum[i]),.cin(cout1[i]),.a(b[i]),.b(temp[i]),.cout(cout1[i+1]));
end
endgenerate
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