在verilog或系统verilog中生成块内部case语句

Question

Is there a way in Verilog or SystemVerilog to insert generate statement inside case statement to generate all the possible input combinations. For example a typical use case would be for a N:1 mux.

case(sel)
  generate
    for(i = 0; i < N; i += 1)
      i: out = q[i];
  endgenerate
endcase

I tried this, but the tool gives error. An alternate syntax is available which is

out <= q[sel];

But, my tool is not understanding this(the mux is fully decoded) and generating combinational loops. I can use if statement to get the expected mux. But, I was wondering if there was a better way to do it.

Answer 1

You can't mix a for and a case like that. If you're just trying to write a multiplexer, have a look at this older question: How to define a parameterized multiplexer using SystemVerilog

The only difference there is that the select signal is supposed to be onehot encoded. For your case you would have:

always_comb begin
out = 'z;
for (int i = 0; i < N; i++) begin
  if(sel == i)
    out = q[i];
end