[英]Is there a simple example of how to generate verilog from Chisel3 module?
I'm looking for a simple howto to convert a simple Chisel3 module in Verilog.我正在寻找一个简单的方法来在 Verilog 中转换一个简单的 Chisel3 模块。
I take Gcd source code given on official web page of chisel.我采用官方 web 页面上给出的 Gcd 源代码。
import chisel3._
class GCD extends Module {
val io = IO(new Bundle {
val a = Input(UInt(32.W))
val b = Input(UInt(32.W))
val e = Input(Bool())
val z = Output(UInt(32.W))
val v = Output(Bool())
})
val x = Reg(UInt(32.W))
val y = Reg(UInt(32.W))
when (x > y) {
x := x -% y
}.otherwise {
y := y -% x
}
when (io.e) {
x := io.a
y := io.b
}
io.z := x
io.v := y === 0.U
}
I can't find a how to write a build.sbt and class instantiation for converting it in Verilog.我找不到如何编写 build.sbt 和 class 实例化以在 Verilog 中进行转换。
Thank you for your interest in Chisel!感谢您对 Chisel 的关注! We generally encourage people to use our chisel-template repo as a starting point for Chisel3 projects: https://github.com/ucb-bar/chisel-template
我们通常鼓励人们使用我们的 chisel-template repo 作为 Chisel3 项目的起点: https : //github.com/ucb-bar/chisel-template
If you want to do the most barebones possible thing.如果你想做最准系统的事情。 Create this build.sbt and put it in the root directory for your project.
创建此 build.sbt 并将其放在项目的根目录中。
scalaVersion := "2.12.12"
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.1"
Put the above GCD source code in GCD.scala and add the following to the file:将上面的 GCD 源代码放在 GCD.scala 中,并将以下内容添加到文件中:
import chisel3.stage.ChiselStage
object GCDDriver extends App {
(new ChiselStage).emitVerilog(new GCD)
}
You can then generate the Verilog by running: sbt "runMain GCDDriver"
.然后,您可以通过运行以下
sbt "runMain GCDDriver"
生成 Verilog: sbt "runMain GCDDriver"
。 The default output directory is the current directory.默认输出目录是当前目录。
You can see what command-line options are available by running sbt "runMain GCDDriver --help"
For example --target-dir
will let you change the target directory您可以通过运行
sbt "runMain GCDDriver --help"
来查看哪些命令行选项可用,例如--target-dir
将让您更改目标目录
You can use jupyter to generate Verilog code conveniently, just like in the Chisel bootcamp.您可以使用 jupyter 方便地生成 Verilog 代码,就像在 Chisel 训练营中一样。 Create a
.ipynb
file with scala kernel and run the setup code first:使用 scala kernel 创建一个
.ipynb
文件并首先运行设置代码:
import $ivy.`edu.berkeley.cs::chisel3:3.+`
import $plugin.$ivy.`edu.berkeley.cs:::chisel3-plugin:3.+`
import chisel3._
then you can generate Verilog code using chisel3.getVerilogString
:然后您可以使用
chisel3.getVerilogString
生成 Verilog 代码:
class Passthrough extends Module {
val io = IO(new Bundle {
val in = Input(UInt(4.W))
val out = Output(UInt(4.W))
})
io.out := io.in
}
println(getVerilogString(new Passthrough))
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