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可在ASIC / FPGA设计中合成查询表分区吗？有道理吗？

[英]Look-Up Table division synthesizable in an ASIC/FPGA design? Makes any sense?

原文 2016-11-10 06:13:59 8 2 fpga/ division/ synthesis/ asic

I was studying the ways to make an efficient FPGA project (toward to become an ASIC design) which include division operations of simple 32 bits binary numbers. 我正在研究一种有效的FPGA项目的方法（即将成为ASIC设计），其中包括简单的32位二进制数的除法运算。

I have found that the most expedite way to do it, is using LUT (Look-up table), than generating a complex division logic. 我发现最快捷的方法是使用LUT（查找表），而不是生成复杂的除法逻辑。 That's fine, however, when I think about ASIC I imagine a physical microchip, with digital logic inside, I can't imagine to put a whole table inside to produce the division. 很好，但是，当我想到ASIC时，我想象的是一个内部带有数字逻辑的物理微芯片，我无法想象将整个表放在里面来产生除法。 I can understand it makes sense in an FPGA because it has a lot of resources including on-chip memory etc, but not on a definitive ASIC. 我可以理解它在FPGA中是有意义的，因为它具有很多资源，包括片上存储器等，但没有确定的ASIC。

My question is, LUT is actually synthesizable in an ASIC design? 我的问题是，LUT实际上可以在ASIC设计中合成吗？ Is this how chips which need division operation, are in fact made? 实际上这是如何进行需要分割运算的芯片吗？

Also, LUT does consumes less area than creating a division module?? 此外，与创建除法模块相比，LUT确实占用更少的面积？

I am quite noob on this, I thank you for your input. 我对此很不满意，谢谢您的投入。

2 个解决方案

General integer division is made using an iterative process, where each iteration generates a number of result bits based on either subtraction or table lookup, similar to when you did division on paper back in school. 一般整数除法是通过迭代过程进行的，每次迭代均基于减法或表查找生成大量结果位，类似于您在学校进行纸面除法时那样。 Specific integer division, for example if the numbers have few digits then a lookup table may be used instead, or if the divisor is an 2 ^ n number, then simple shifting may be used maybe combined with addition for rounding. 特定的整数除法，例如，如果数字位数少，则可以使用查找表代替；或者，如果除数是2 ^ n数，则可以将简单移位与加法结合使用以进行舍入。 So actual implementation of division actually depends on the arguments, and speed/size requirements. 因此，除法的实际实现实际上取决于参数和速度/大小要求。

Regarding your FPGA to ASIC conversion, then the LUTs in the FPGA is just a flexible way to implement general purpose combinational circuits, since an eg 4-input LUT can implement all outputs for a 4-input function. 关于从FPGA到ASIC的转换，FPGA中的LUT只是实现通用组合电路的一种灵活方式，因为例如4输入LUT可以实现4输入功能的所有输出。 When you synthesize logical expressions to an FPGA, then the result will be a LUT representation since that is the building blocks available in an FPGA, but if you synthesize logical expressions to an ASIC, then the result will usually be a discrete gate representation since that is the building blocks available in an ASIC. 当您将逻辑表达式合成到FPGA时，结果将是LUT表示形式，因为这是FPGA中可用的构造块，但是如果您将逻辑表达式合成到ASIC，则结果通常将是离散门表示形式，因为是ASIC中可用的构建块。 The ASIC implementation is smaller and faster (for same technology), since the general purpose LUT overhead is avoided, however at the loss of the FPGA flexibility. ASIC的实现方式更小，更快（对于相同的技术），因为避免了通用LUT开销，但是却失去了FPGA的灵活性。

Synthesis become popular in FPGA designers. 综合在FPGA设计人员中变得很流行。 Everything you need to know about LUT based architecture is a transistor level design techniques which required set of skills. 您需要了解的有关基于LUT的体系结构的所有知识都是晶体管级设计技术，它需要一组技能。

I personally go with verilog netlist file with netgen command. 我个人使用netgen命令处理verilog网表文件。 You can go FPGA - LUT Architecture Optmization 您可以使用FPGA-LUT架构优化