Makefile混乱

Question

I'm new to makefiles, but I finally managed to get one working for a project I'm working on. The original goal was to search the folder "Source" for any CPP files, then create an Object file in the folder Products/Objs. Instead, it finds the CPP files, but OBJECT_FILES is the same as SOURCE_FILES, and I'm not sure how it's working. It doesn't generate any .o files (that I could see), but still compiles successfully. Super confused but would love some help. Thanks!

##########################################
#           Editable options             #
##########################################

# Program Name
EXECUTABLE=net

# Compiler options
CC=g++
CFLAGS=
LDFLAGS=

# Folders
SRC=Source
OBJ=Products/Objs

#########################################################
#                     Do Not Touch This                 #
#########################################################
SOURCE_FILES := $(shell find $(SRC)/ -type f -name '*.cpp')

## This should not work
OBJECT_FILES := $(SOURCE_FILES: $(SRC)/%.cpp=%.o)
## Like at all --> It's the same as SOURCE_FILES
## But I guess???

build: $(EXECUTABLE)

## Deletes the executable (assumes small compile time)
clean:
    @rm -r -f $(shell find $(SRC)/ -type f -name '*.o')
    @rm $(EXECUTABLE)

.PHONY: build clean

$(EXECUTABLE): $(OBJECT_FILES)
    @$(CC) $(LDFLAGS) -o $@ $^
    @echo "Build successful!"

$(OBJECTS_FILES): %.o : $(SRC)/%.cpp
    @$(CC) $(CFLAGS) -o -c $@ $^

Answer 1

Well first you have a typo; you create a variable OBJECT_FILES :

OBJECT_FILES := $(SOURCE_FILES: $(SRC)/%.cpp=%.o)

Also you shouldn't use spaces here (after the : ). Then you use a variable named OBJECTS_FILES instead:

$(OBJECTS_FILES): %.o : $(SRC)/%.cpp

That variable is empty so this is essentially a no-op.

Your compiler invocation is wrong. The word after the -o option is the file the output should go to; yours is:

@$(CC) $(CFLAGS) -o -c $@ $^

which means that the output of this command is going to the file -c . Then the input is an object file that doesn't exist... most likely you'll get an error. Also you only want to pass the source file to the compiler, not all the other prerequisites (headers etc.) This should be:

@$(CC) $(CFLAGS) -c -o $@ $<