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(VHDL)尝试从阵列输出时收到错误

[英](VHDL) I'm Receiving an Error When Trying to Output from an Array

I'm trying to output data inside an array to the 7-segment display on my DE1-SoC board. 我试图将阵列内的数据输出到DE1-SoC板上的7段显示器。

Here are my variables: 这是我的变量:

display : out std_logic_vector (6 downto 0);

type bigDisplay is array (0 to 4, 0 to 6) of bit;

signal displayArray : bigDisplay;

Here is the code: 这是代码:

display <= displayArray (0, 6-0);

This is the error I receive: 这是我收到的错误:

Error (10381): VHDL Type Mismatch error at Final_Project.vhd(326): indexed name returns a value whose type does not match "std_logic_vector", the type of the target expression

So, I'm guessing I need to convert my bit array to output to the std_logic_vector? 所以,我猜我需要将我的位数组转换为输出到std_logic_vector吗? How should I do this? 我应该怎么做?

Any particular reason for using bit ? 使用bit任何特殊原因? You can just as easily create an array of std_logic_vector : 您可以轻松地创建一个std_logic_vector数组:

type bigDisplay is array(0 to 4) of std_logic_vector(6 downto 0);
signal displayArray : bigDisplay;

Then simply (after initializing displayArray with values, of course): 然后简单地(当然,在用值初始化displayArray之后):

display <= displayArray(0);

Etc, or whatever index you desire, in order to assign values from your array to the display. 等等,或者您想要的任何索引,以便将数组中的值分配给显示。

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