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如何在 RISC-V 汇编中使用向量操作

[英]How to use vector operations in RISC-V Assembly

原文 2019-02-01 11:04:00 1 2 assembly/ simd/ riscv

I am trying to exploit vector operations in RISC-V Assembly, in particular I need to compile my source code with arch RV64iV or RV64GV.我正在尝试利用 RISC-V 程序集中的向量操作，特别是我需要使用 arch RV64iV 或 RV64GV 编译我的源代码。 I am using riscv64-unknown-elf- toolchain, with the following parameters:我正在使用 riscv64-unknown-elf- 工具链，具有以下参数：

riscv64-unknown-elf-gcc -o test -march=rv32iv test.s riscv64-unknown-elf-gcc -o test -march=rv32iv test.s

but I get the following error:但我收到以下错误：

Assembler messages: Fatal error: -march=rv32iv: unsupported ISA subset `v'汇编程序消息：致命错误：-march=rv32iv：不支持的 ISA 子集“v”

Thanks谢谢

2 个解决方案

As of February 2019 there is no standard RISC-V vector extension, which means there is no support in standard RISC-V toolchains.截至 2019 年 2 月，没有标准的 RISC-V 矢量扩展，这意味着标准 RISC-V 工具链不支持。 There are various drafts of the vector extension floating around, but nothing supported by software.有各种各样的矢量扩展草案，但没有软件支持。

As of early 2020, the RISC-V vector extension "V" specification is at version 0.8 and still has draft status.到 2020 年初，RISC-V 矢量扩展“V”规范是 0.8 版，仍处于草案状态。

However, there are "V" ports of the GNU gcc/binutils available and the Spike RISC-V simulator supports "V" 0.8, as well.但是，有可用的 GNU gcc/binutils 的“V”端口，Spike RISC-V 模拟器也支持“V”0.8。 The README of the "V" spec links to the relevant branches . “V”规范的自述文件链接到相关分支。

I recently published some notes on how to get started with RISC-V "V" 0.8 development, eg how to build the right toolchain, related components, assemble, compile "V" code and how to test it with Spike.我最近发表了一些关于如何开始 RISC-V "V" 0.8 开发的笔记，例如如何构建正确的工具链、相关组件、组装、编译“V”代码以及如何使用 Spike 对其进行测试。