[英]Verilog case statement is always true
Verilog case statmenet expression is always true Verilog案例statmenet表达式始终为true
module test(input clk,
input reset,
output reg[3:0] ledss
);
reg[31:0] dataread;
always @(posedge clk)
begin
case(dataread)
32'b1010101010101010101:ledss='b1010;
endcase
end
endmodule
dont understand why this line executed 不明白为什么执行这条线
32'b1010101010101010101:ledss='b1010;
leds is on same pattern 1010 LED处于相同模式1010
also after executing this code , leds not on 同样在执行此代码后,LED不亮
module test(input clk,
input reset,
output reg[3:0] ledss
);
reg[31:0] dataread;
always @(posedge clk)
begin
if(dataread==32'b1010101010101010101) ledss='b1010;
end
endmodule
but if i execute this,leds is on ,pattern 1010 但是,如果我执行此操作,指示灯将亮起,模式1010
module test(input clk,
input reset,
output reg[3:0] ledss
);
reg[31:0] dataread;
always @(posedge clk)
begin
case(dataread)
32'b101010101010:
begin
if(dataread==32'b101010101010) ledss='b1010;
end
endcase
end
endmodule
dont understand how case statement works in verilog 不了解case语句在verilog中如何工作
I believe you are skipping Verilog simulation and loading your code directly to FPGA. 我相信您正在跳过Verilog仿真,而是直接将代码加载到FPGA。
In simulation. 在模拟中。
ledss
would be X until the patter match is satisfied (both case
or if
). 直到满足模式匹配(无论是
case
还是if
), ledss
都是X。 In the provided code dataread
is never assigned so it will be X, therefore in simulation ledss
will always be X. In your pastebin links you have dataread
driven by a ROM output, so it will have a know output that might match the checking condition. 在提供的代码中,永远不会分配
dataread
,因此它将是X,因此在模拟ledss
中将始终是X。在pastebin链接中,数据dataread
是由ROM输出驱动的,因此它将有一个与检查条件匹配的已知输出。
FPGA synthesizes your RTL and typically goes through some optimization. FPGA合成您的RTL,通常会进行一些优化。
ledss
is not explicitly initialized and has only one possible value if ever assigned. ledss
没有显式初始化,并且只有一个可能的值(如果已分配)。 Because of this the optimizer might assume the initial value is don't care, then simplify logic by choosing the initial value to be the same as the only possible value it can be assigned to. 因此,优化器可能会认为初始值无关紧要,然后通过选择初始值与可以分配给它的唯一可能值相同来简化逻辑。 Or it might assume the initial value is 0 and keep the logic.
或者可以假定初始值为0并保留逻辑。 For this scenario in general,
case
tends the follow the former and if
tends to follow the latter. 通常,对于这种情况,
case
倾向于遵循前者, if
倾向于遵循后者。 Though your code is functionally equivalent, it is uncommon to have a case-statement with only one condition. 尽管您的代码在功能上是等效的,但只包含一个条件的案例陈述并不常见。
I suggest you improve your coding style so your intended behavior is more explicitly understood by the synthesizer and anyone reading your code. 我建议您改善编码风格,以便合成器和任何阅读您的代码的人都能更清楚地理解您的预期行为。 Bellow are some suggestions.
波纹管是一些建议。 Remember to assign
dataread
to a known value. 请记住将数据
dataread
分配给一个已知值。 (Note: replaced 32'b1010101010101010101
with the equivalent 32'h0005_5555
for human readability) (注:代替
32'b1010101010101010101
用等价32'h0005_5555
易读性)
always @(posedge clk)
begin
case(dataread)
32'h0005_5555 : ledss <= 4'b1010;
default : ledss <= 4'b1111;
endcase
end
Or equivalent: 或同等学历:
always @(posedge clk)
begin
if (dataread == 32'h0005_5555)
ledss <= 4'b1010;
else
ledss <= 4'b1111;
end
If you want ledss
to keep the 1010 patter after assignment, then you could do: 如果您希望
ledss
在分配后保持1010模式,则可以执行以下操作:
always @(posedge clk)
begin
if (reset) begin
ledss <= 4'b1111;
end
case(dataread)
32'h0005_5555 : ledss <= 4'b1010;
endcase
end
Or equivalent: 或同等学历:
always @(posedge clk)
begin
if (reset) begin
ledss <= 4'b1111;
end
else if (dataread == 32'h0005_5555) begin
ledss <= 4'b1010;
end
end
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