[英]How to use 32-bit w registers in ARM aarch64 GCC inline assembly?
I can use 64-bit registers for example as in:我可以使用 64 位寄存器,例如:
#include <assert.h>
#include <inttypes.h>
int main(void) {
uint64_t io = 1;
__asm__ (
"add %[io], %[io], 1;"
: [io] "+r" (io)
:
:
);
assert(io == 2);
}
which compiles and disassembles with:它编译和反汇编:
aarch64-linux-gnu-gcc -ggdb3 -o main.out main.c
gdb-multiarch -batch -ex 'disassemble/rs main' main.out
to a 64-bit register as expected:按预期到 64 位寄存器:
6 __asm__ (
0x0000000000000744 <+16>: a0 0f 40 f9 ldr x0, [x29, #24]
0x0000000000000748 <+20>: 00 04 00 91 add x0, x0, #0x1
0x000000000000074c <+24>: a0 0f 00 f9 str x0, [x29, #24]
How to use 32-bit registers such as w0 instead?如何改用 w0 等 32 位寄存器?
Tested on Ubuntu 18.04, GCC 7.4.0.在 Ubuntu 18.04、GCC 7.4.0 上测试。
It can be done by adding the w
in front of the %
, eg:可以通过在%
前面添加w
来完成,例如:
#include <assert.h>
#include <inttypes.h>
int main(void) {
uint32_t io = 1;
__asm__ (
"add %w[io], %w[io], 1;"
: [io] "+r" (io)
:
:
);
assert(io == 2);
}
which now disassembles to the desired 32-bit version:现在反汇编为所需的 32 位版本:
6 __asm__ (
0x0000000000000744 <+16>: a0 1f 40 b9 ldr w0, [x29, #28]
0x0000000000000748 <+20>: 00 04 00 11 add w0, w0, #0x1
0x000000000000074c <+24>: a0 1f 00 b9 str w0, [x29, #28]
This could have been somewhat guessed from: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100067_0612_00_en/qjl1517569411293.html since the ARM compiler 6 is LLVM based, and LLVM syntax is mostly GCC based.这可能有点猜测: http : //infocenter.arm.com/help/index.jsp? topic=/ com.arm.doc.100067_0612_00_en/qjl1517569411293.html因为 ARM 编译器 6 基于 LLVM 和 LLVM 语法主要基于 GCC。
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