如何在时钟的 posedge 和 negedge 设置信号？

Question

I'm trying to implement a controller with the function that sends out the same clock signal as its input clock. But the controller can also halt the output signal if needed. I'm implementing it on Xilinx ISE.

My idea is: At the negedge of the input clock, the output clock signal set to 0. At the posedge of the input clock, if I want to send out the clock I'll set the output clock to 1, but if I want to halt the output clock, I'll set the output clock to 0 so other devices (all posedge-triggered) won't detect the posedge.

Here's my design:

module controller(
    input clk_in,
    input reset,
    output clk_out
    //and other ports
);
    always @(negedge clk_in)
      clk_out<=0;

    always @(posedge clk_in)
      if(reset)
        clk_out<=1;
      else
      begin
        case(cases)
          case1:
          begin
            //do something and halt the output clock
            clk_out<=0;
          end
          case2:
          begin
            //do something and continue the output clock
            clk_out<=1;
          end
        endcase
      end       

When I synthesized the design I had an error saying the signal clk_out is connected to multiple drivers. Is there any way to solve it?

Answer 1

You have two different always blocks which drive the same signal clk_out. This is what synthesis tells you about. All signals in a synthesizable rtl must be driven from a single block only.

It looks like you are trying to create some type of a gated clock. Instead of going through the trouble of detecting negedges of the clock, which most likely will not be synthesizable as well, you can use a simple logic to do so:

    always @*
        clk_out = enable & clk_in;

You just have to figure out how to generate enable .

BTW, never use NBAs (<=) in generating clock signals or you end up with clock/data race conditions.