Makefile 将源列表编译到自定义目录

Question

I have this makefile:

IDIR = include
SDIR = src
ODIR = obj
BDIR = build

DEPS = $(shell find $(IDIR)/ -name '*.hpp')
SRCS = $(shell find $(SDIR)/ -name '*.cpp')
OBJS = $(patsubst %.cpp,$(ODIR)/%.o,$(notdir $(SRCS)))
BIN = main

CPPC = g++
CFLAGS = -Wall -c

all: dir $(BDIR)/$(BIN)
    @echo Finished compiling $(BIN)

dir:
    mkdir -p $(BDIR)
    mkdir -p $(ODIR)

$(BDIR)/$(BIN): $(OBJS)
    $(CPPC) $^ -o $@

$(OBJS): $(SRCS)
    $(CPPC) $(CFLAGS) $^ -o $@

clean:
    rm -rf $(BDIR) $(ODIR)

When I try to make, I get the following error:

mkdir -p build
mkdir -p obj
g++ -Wall -c src/sdk/tcp/Tcp.cpp src/sdk/socket/Socket.cpp src/Main.cpp -o obj/Tcp.o
g++: fatal error: cannot specify ‘-o’ with ‘-c’, ‘-S’ or ‘-E’ with multiple files
compilation terminated.
make: *** [Makefile:27: obj/Tcp.o] Error 1

My question is, is it possible to achieve what I am trying with this makefile? Going through each source file in $(SRCS), and compile the object file directly inside the obj directory with just the basename. An example of obj directory after a successful compilation:

         obj
  /       |        \
 /        |         \
Tcp.o   Socket.o    Main.o

Answer 1

Your $(OBJS) rule is wrong.

There are (at least) two ways to do this.

You could write a pattern rule and use vpath to locate the sources:

vpath %.cpp $(dir $(SRCS))

$(OBJS): obj/%.o: %.cpp
    $(CPPC) $(CFLAGS) $^ -o $@

Or you could generate a rule for each object:

define template
$(patsubst %,obj/%.o,$(notdir $(1))): $(addsuffix .cpp,$(1))
    echo $(CPPC) $(CFLAGS) $$^ -o $$@
endef

$(foreach src,$(SRCS),$(eval $(call template,$(basename $(src)))))