我如何确定编译器何时缓存值而不是从正确的寄存器或内存位置读取它们？

Question

I am running into a problem where I am polling flags in an ARM processor for SPI transmission completion and it hangs in the while loop. I am not entirely sure what is going on and I suspect that the compiler is not actually fetching the value stored in the register.

//LPSPI1 is part of the ARM CMSIS ABI

void WriteCmdDataLCD(uint8_t *data_buffer, uint32_t data_length)
{
volatile uint32_t inc = 0;
...
while(inc < data_length)
{
    LPSPI1->TDR = *(data_buffer+inc);
    while(((LPSPI1->SR & LPSPI_SR_TDF_MASK) >> LPSPI_SR_TDF_SHIFT) == 0);
    LPSPI1->SR = LPSPI_SR_TDF_MASK;
    inc++;

}
...

The LPSPI1 TX FIFO is 16 words deep, if I write 16 words or less to this FIFO there is no problem. However, when I write more than 16 then it gets stuck in that while loop. Presumably because TDF (Transmission Done Flag) never evaluates to 1 (for complete). The debugger is too invasive because if I break program execution and restart it, it gets beyond that point.

ICACHE and DCACHE are disabled. I am at a loss for next steps.

If it matters, the ARM processor is the I.MXRT1060.

Edit: So this is a phantom problem and is hardware behavior related. I need to rethink how to use this peripheral.

Answer 1

How do I determine when the compiler is caching values

The compiler is not caching anything (maybe something internal when the compiler is run) The hardware when you run the compiled program might cache something.

ICACHE and DCACHE are disabled. I am at a loss for next steps.

Then nothing will be cached and your problem simply does not exist. But even if you enable them Cortex-M7 guarantees that the core accesses to the memory is coherent. In your case, you poll for the data and core reads (and writes) hardware registers and memory.

If you use DMA with the cache ON - you will have to invalidate the cache before accessing the data. But it is not the case here.

There is a lot of confusion about the volatile in this question and answers.

To clarify:

1. volatile uint32_t inc = 0; - inc does not have to be volatile.
2. Hardware registers are declared as volatile in the NXP provided headers. Nothing to worry about. Those headers are used by thousands of programmers around the world.
3. data buffers do not have to be volatile.

Your check can be simplified to:

while(!(LPSPI1->SR & LPSPI_SR_TDF_MASK));

The data register write is incorrect. It shuld be:

*(volatile uint8_t *)&LPSPI1->TDR = *(data_buffer+inc);

otherwise, the compiler will generate 32 bit write instruction and 4 values will be stored in the FIFO instead of one (your data + 3 zero bytes). It is a very common beginners trap. Here you can see the difference in the generated code: https://godbolt.org/z/x9Knd5

The order of operation is incorrect (you should first check if you can write, then write) it shuld be:

while(!(LPSPI1->SR & LPSPI_SR_TDF_MASK));
*(volatile uint8_t *)&LPSPI1->TDR = *(data_buffer+inc);

The question of why it stops in the while loop is almost impossible to answer without the full code and access to your hardware. I can only guess. Probably the peripheral is not correctly configured and/or some error conditions are detected. You never check the error flags.

Presumably because TDF (Transmission Done Flag) It is Transmit Data Flag and it does not indicate the end of the transmission.

There is another flag called TCF used to indicate the end of the transfer. I strongly advise to read carefully and with understanding the relevant chapter of the Referance Manual , then start to write the software

Answer 2

How do I determine when the compiler is caching values and not reading them from the proper registers or memory locations?

The compiler might want to "cache" all values which are not declared with volatile .

You might create a test:

unsigned int maybe_cached = REGISTER;
volatile unsigned int never_cached = REGISTER;

/* some code */

if(maybe_cached != never_cached){
    /* something had been cached */
}

PS you should use volatile at atleast for all asynchronous operations.