如何在 VHDL 中为 std_logic_vector 赋值？

Question

I am trying to assign value to OUTPUT std_logic_vector in the below code, but it gives me errors that

COMP96 ERROR COMP96_0143: "Object "OUTPUT" cannot be written." "design.vhd" 20 18

COMP96 ERROR COMP96_0143: "Object "OUTPUT" cannot be written." "design.vhd" 21 18

COMP96 ERROR COMP96_0143: "Object "OUTPUT" cannot be written." "design.vhd" 22 18

COMP96 ERROR COMP96_0143: "Object "OUTPUT" cannot be written." "design.vhd" 23 20

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
 
entity demux_1to4 is
 port(
 I : IN STD_LOGIC;
 S: IN STD_LOGIC_VECTOR(1 downto 0);
 OUTPUT: IN STD_LOGIC_VECTOR(3 downto 0)
 );
end demux_1to4;
 
architecture bhv of demux_1to4 is
begin
process (I,S) is
begin
    case(S) is 
    when "00" => OUTPUT <= "0001" ;
    when "01" => OUTPUT<= "0010" ;
    when "10" => OUTPUT<= "0100" ;
    when others => OUTPUT<= "1000" ;
    end case ; 
end process;
end bhv;

Where I am doing wrong?

Answer 1

Error indicates that "Object "OUTPUT" cannot be written."

OUTPUT is declared as an input port in the entity. To write/assign values, it must be an output port. (or an internal signal in general).

OUTPUT: OUT STD_LOGIC_VECTOR(3 downto 0)

 port(
 I     : IN STD_LOGIC;
 S     : IN STD_LOGIC_VECTOR(1 downto 0);
 OUTPUT: OUT STD_LOGIC_VECTOR(3 downto 0)
 );