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Makefile % match-anything 规则选择“Makefile”目标

[英]Makefile % match-anything rule picks up "Makefile" target

I'm trying to write a universal Makefile to sync the source tree with some remote host, ssh into it and execute make there, forwarding any targets or variable overrides我正在尝试编写一个通用 Makefile 以将源树与某个远程主机 ssh 同步到其中并在那里执行 make,转发任何目标或变量覆盖

So far I came up with this:到目前为止,我想出了这个:

HOST ?= host
DIR ?= ~/dev

SRC = src

all:

.PHONY: sync
sync:
    rsync -azP --exclude ".*/" --exclude ".*" $(SRC)/ $(HOST):$(DIR)

%: sync
    ssh $(HOST) 'cd $(DIR) && make $@ MAKEFLAGS=$(MAKEFLAGS)'

It works great as long as I omit sync in the dependency list of % target.只要我在% target 的依赖项列表中省略sync ,它就可以很好地工作。 Once I add it back in, Makefile target is picked up for some reason, causing it to ssh into the remote machine and run make Makefile , which is not a valid target or expected behaviour一旦我重新添加它, Makefile目标由于某种原因被拾取,导致它 ssh 进入远程机器并运行make Makefile ,这不是一个有效的目标或预期的行为

To clarify, I don't specify Makefile as a target myself.澄清一下,我自己并没有将Makefile指定为目标。 I do我愿意

make
make clean

All of which result in Makefile target being run regardless所有这些都会导致Makefile目标运行,无论

GNU make automatically attempts to rebuild the makefile(s) before building the designated targets or default target . GNU make在构建指定目标或默认目标之前自动尝试重新构建 makefile Other make implementations do not necessarily do this.其他make实现不一定这样做。 The GNU make manual contains this advice about your particular problem: GNU make手册包含有关您的特定问题的建议:

If you know that one or more of your makefiles cannot be remade and you want to keep make from performing an implicit rule search on them, perhaps for efficiency reasons, you can use any normal method of preventing implicit rule look-up to do so.如果您知道您的一个或多个 makefile 无法重新制作,并且您想阻止 make 对它们执行隐式规则搜索,也许出于效率原因,您可以使用任何防止隐式规则查找的常规方法来执行此操作。 For example, you can write an explicit rule with the makefile as the target, and an empty recipe [...]例如,您可以使用 makefile 作为目标编写一个显式规则,以及一个空配方 [...]

The empty recipe approach would be to add a rule such as this:空配方方法是添加如下规则:

Makefile: ;

With that present in your makefile (and the file's name being Makefile ), when make looks for a rule with which to rebuild Makefile it will choose that explicit, empty rule instead of the match-anything wildcard rule.在您的 makefile 中存在该文件(并且文件名为Makefile ),当make查找用于重建Makefile的规则时,它将选择明确的通配符规则,空的规则。 It would be a little more robust to write that like this, however:但是,这样写会更健壮一些:

$(MAKEFILE_LIST): ;

The MAKEFILE_LIST variable contains the names of all the makefiles that make read, so it will cover you even if you add include directives to your makefile or if you access it from a different directory or via a different name by use of the -f command-line option. MAKEFILE_LIST变量包含所有make读取的 makefile 的名称,因此即使您将include指令添加到 makefile 或者如果您从不同的目录或使用-f命令通过不同的名称访问它,它也会覆盖您 -线选项。

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