I'm trying to write a universal Makefile to sync the source tree with some remote host, ssh into it and execute make there, forwarding any targets or variable overrides
So far I came up with this:
HOST ?= host
DIR ?= ~/dev
SRC = src
all:
.PHONY: sync
sync:
rsync -azP --exclude ".*/" --exclude ".*" $(SRC)/ $(HOST):$(DIR)
%: sync
ssh $(HOST) 'cd $(DIR) && make $@ MAKEFLAGS=$(MAKEFLAGS)'
It works great as long as I omit sync
in the dependency list of %
target. Once I add it back in, Makefile
target is picked up for some reason, causing it to ssh into the remote machine and run make Makefile
, which is not a valid target or expected behaviour
To clarify, I don't specify Makefile
as a target myself. I do
make
make clean
All of which result in Makefile
target being run regardless
GNU make
automatically attempts to rebuild the makefile(s) before building the designated targets or default target . Other make
implementations do not necessarily do this. The GNU make
manual contains this advice about your particular problem:
If you know that one or more of your makefiles cannot be remade and you want to keep make from performing an implicit rule search on them, perhaps for efficiency reasons, you can use any normal method of preventing implicit rule look-up to do so. For example, you can write an explicit rule with the makefile as the target, and an empty recipe [...]
The empty recipe approach would be to add a rule such as this:
Makefile: ;
With that present in your makefile (and the file's name being Makefile
), when make
looks for a rule with which to rebuild Makefile
it will choose that explicit, empty rule instead of the match-anything wildcard rule. It would be a little more robust to write that like this, however:
$(MAKEFILE_LIST): ;
The MAKEFILE_LIST
variable contains the names of all the makefiles that make
read, so it will cover you even if you add include
directives to your makefile or if you access it from a different directory or via a different name by use of the -f
command-line option.
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