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Scala 凿纹波进位加法器语法

[英]Scala Chisel Ripple Carry Adder Syntax

im trying to design the following Ripple Carry Adder made of Fulladers.我正在尝试设计以下由 Fulladers 制成的 Ripple Carry Adder。 I tried a lot so far, but I'm struggling with Chisel Syntax.到目前为止我尝试了很多,但我正在努力使用凿子语法。 Could someone help me out and point out what I'm doing wrong?有人可以帮助我并指出我做错了什么吗? This is my Code below:这是我的代码如下:

class RcaAdder(val n:Int) extends Module {
  val io = IO(new Bundle {
   val a    = Input(UInt(n.W))
   val b    = Input(UInt(n.W))
   val cin  = Input(UInt(1.W))
   val sum  = Output(UInt(n.W))
   val cout = Output(UInt(1.W))
  })


  //For loop
  for(i <- 0 to n){

   val fulladder = Module(new FullAdder())
   fulladder.io.a := io.a(i)
   fulladder.io.b := io.b(i)

   if(i == 0){
     fulladder.io.cin := io.cin    
   }else{
     fulladder.io.cin := io.cout
   }

   io.cout := fulladder.io.cout
   io.sum(i) := fulladder.io.sum
  }
}

Which gets me the following error:这让我得到以下错误:

Exception in thread "main" chisel3.internal.ChiselException: Cannot reassign to read-only Bool(OpResult in RcaAdder)

I assume it has something to do with the " io.sum(i):=.. "我认为它与“ io.sum(i):=.. ”有关

Please help me out!请帮帮我! Thank you so much!太感谢了!

You are very close to getting it working.你非常接近让它工作。 One problem you are having is that you cannot assign to a bit subset on the left hand side of := .您遇到的一个问题是您无法分配给:=左侧的位子集。 One way of getting around this is to create a Vec of UInt(1.W) and then use that as the RHS as a single as a single assignment.解决此问题的一种方法是创建UInt(1.W)Vec ,然后将其用作 RHS 作为单个分配。 I think you have a problem with your if s, I'd recommend using foldLeft instead of for because it provides a mechanism of accessing the previous elements.我认为您的if有问题,我建议您使用 foldLeft 而不是for因为它提供了访问先前元素的机制。 Put that all together and I think what you want is something like this.把这些放在一起,我认为你想要的是这样的东西。

class RcaAdder(n: Int) extends Module {
  val io = IO(new Bundle {
    val a    = Input(UInt(n.W))
    val b    = Input(UInt(n.W))
    val cin  = Input(UInt(1.W))
    val sum  = Output(UInt(n.W))
    val cout = Output(UInt(1.W))
  })

  val outBits = Wire(Vec(n, UInt(1.W)))

  io.cout := (0 until n).foldLeft(io.cin) { case (carry, index) =>
    val fullAdder = Module(new FullAdder)
    fullAdder.io.a := io.a(index)
    fullAdder.io.b := io.b(index)
    fullAdder.io.cin := carry
    outBits(index) := fullAdder.io.sum
    fullAdder.io.cout.    // This will be passed as carry to the next interation
  }
  io.sum := outBits.asUInt()
}

I've added a working test example here on scastie .在 scastie 上添加了一个工作测试示例。 Good luck and welcome to Chisel祝你好运,欢迎来到 Chisel

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