chisel 中如何解释这种语法？

Question

I am learning chisel and rocket-chip. I recently found an unreadable syntax in the rocket / RocketCore.scala file.

val perfEvents = new EventSets(Seq(
new EventSet((mask, hits) => Mux(mask(0), wb_xcpt, wb_valid && pipelineIDToWB((mask & hits).orR)), Seq(
  ("exception", () => false.B),
  ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp),
  ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp),
  ("amo", () => Bool(usingAtomics) && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))),
  ("system", () => id_ctrl.csr =/= CSR.N),
  ("arith", () => id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)),
  ("branch", () => id_ctrl.branch),
  ("jal", () => id_ctrl.jal),
  ("jalr", () => id_ctrl.jalr))
  ++ (if (!usingMulDiv) Seq() else Seq(
    ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & ALU.FN_DIV) =/= ALU.FN_DIV),
    ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & ALU.FN_DIV) === ALU.FN_DIV)))
  ++ (if (!usingFPU) Seq() else Seq(
    ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen),
    ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen),
    ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23),
    ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3),
    ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3),
    ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div || io.fpu.dec.sqrt)),
    ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst || io.fpu.dec.fma || io.fpu.dec.div || io.fpu.dec.sqrt))))),
new EventSet((mask, hits) => (mask & hits).orR, Seq(
  ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem || id_mem_hazard && mem_ctrl.mem || id_wb_hazard && wb_ctrl.mem),
  ("long-latency interlock", () => id_sboard_hazard),
  ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N || id_mem_hazard && mem_ctrl.csr =/= CSR.N || id_wb_hazard && wb_ctrl.csr =/= CSR.N),
  ("I$ blocked", () => icache_blocked),
  ("D$ blocked", () => id_ctrl.mem && dcache_blocked),
  ("branch misprediction", () => take_pc_mem && mem_direction_misprediction),
  ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked),
  ("flush", () => wb_reg_flush_pipe),
  ("replay", () => replay_wb))
  ++ (if (!usingMulDiv) Seq() else Seq(
    ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul || ex_ctrl.div) || id_mem_hazard && (mem_ctrl.mul || mem_ctrl.div) || id_wb_hazard && wb_ctrl.div)))
  ++ (if (!usingFPU) Seq() else Seq(
    ("fp interlock", () => id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu)))),
new EventSet((mask, hits) => (mask & hits).orR, Seq(
  ("I$ miss", () => io.imem.perf.acquire),
  ("D$ miss", () => io.dmem.perf.acquire),
  ("D$ release", () => io.dmem.perf.release),
  ("ITLB miss", () => io.imem.perf.tlbMiss),
  ("DTLB miss", () => io.dmem.perf.tlbMiss),
  ("L2 TLB miss", () => io.ptw.perf.l2miss)))))

When using class EventSet, I did not find the definition of mask and hits.

Answer 1

That is a pretty intimidating piece of code. Breaking it down

• perfEvents is assigned to be an instance of EventSets
• EventSets requires a single parameter
  • class EventSets(val eventSets: Seq[EventSet])
  • So you see a Seq of EventSet begin created.
• EventSet requires two parameters
  • class EventSet(gate: (UInt, UInt) => Bool, events: Seq[(String, () => Bool)])
  • First: A function of two UInts that returns a Bool
  • Second: A Seq of 2 tuples of String and a function with no parameters that returns a Bool
  • So you see a long sequence of these tuples being defined.
  • NOTE: The sequence of (String, () => Bool()) needs to be different depending on configuration parameters like usingMulDiv
    • Thus you see the construct ++ (if (.. a couple of times.
    • This uses if conditionally add different subsequences of tuples to the EventSet parameter it is constucting.

I hope that helps. This is a whole lot of stuff that is probably going to be either ugly and short or clearer and really long and verbose. It may help a little to run this through a formatter. Here's a bit of that.

val perfEvents = new EventSets(
  Seq(
    new EventSet(
      (mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)),
      Seq(
        ("exception", () => false.B),
        ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp),
        ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp),
        ("amo",
         () =>
           Bool(usingAtomics) && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))),
        ("system", () => id_ctrl.csr =/= CSR.N),
        ("arith",
         () =>
           id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)),
        ("branch", () => id_ctrl.branch),
        ("jal", () => id_ctrl.jal),
        ("jalr", () => id_ctrl.jalr)
      )
        ++ (if (!usingMulDiv) Seq()
            else
              Seq(

Answer 2

mask and hits are just arguments of the lambda passed to the EventSet constructor, the (mask, hits) => ... part is their definition (or declaration, if you prefer). If you look at EventSet source you can see the lambda is called gate and used only in this method:

def check(mask: UInt) = gate(mask, hits)

So mask will be the argument of check and hits come from

def hits = events.map(_._2()).asUInt

In this case, for the first EventSet you'll get something like

Seq(
  false.B,
  id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp,
  ...
).asUInt