[英]Conditionnal Module instantiation un Chisel
I'm trying to instanciate one of two chisel Module according to boolean parameter.我正在尝试根据 boolean 参数实例化两个凿子模块之一。
val useLib = true
val myModule = if(useLib) Module(new MyModule1()) else Module (new MyModule2())
But that doesn't work.但这不起作用。 Chisel doesn't recognize io
interface: Chisel 不识别io
接口:
[error] /path/to/source/mysource.scala:59:13: value io is not a member of Any
[error] myModule.io.pdm <> io.pdm
[error] ^
And of course, MyModule1()
and MyModule2()
have same io interfaces.当然, MyModule1()
和MyModule2()
具有相同的 io 接口。
Is it possible to conditionnaly instantiate Module() as we do with preprocessor in C or C++?是否可以像我们在 C 或 C++ 中使用预处理器一样对 Module() 进行条件实例化?
I've written a new doc about upgrading from Chisel 3.4 to 3.5 that deals with this issue.我写了一篇关于从 Chisel 3.4 升级到 3.5 的新文档来处理这个问题。 It's not live on the website yet but will be once Chisel 3.5.0-RC2 is released.它尚未在网站上发布,但将在 Chisel 3.5.0-RC2 发布后发布。 Here's a link to the doc: https://gist.github.com/jackkoenig/4949f6a455ae74923bbcce10dbf846b5#value-io-is-not-a-member-of-chisel3module这是文档的链接: https://gist.github.com/jackkoenig/4949f6a455ae74923bbcce10dbf846b5#value-io-is-not-a-smember-of-chillmodule3
In sort, from Scala's perspective, MyModule1
and MyModule2
actually do not have the same interface, even though they are structurally the same.从 Scala 的角度来看, MyModule1
和MyModule2
实际上并不具有相同的接口,尽管它们在结构上是相同的。 The trick is to factor out that interface into a named Bundle
class and then use that in each of those modules.诀窍是将该接口分解到一个名为Bundle
class 的名称中,然后在每个模块中使用它。 You then make each Module
extend a trait
that has that interface, and then Scala will know that the interfaces are the same.然后让每个Module
扩展一个具有该接口的trait
,然后 Scala 将知道接口是相同的。
For more information and examples, see the above linked doc.有关更多信息和示例,请参阅上面的链接文档。
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