为什么“cmd_$@”是构建时的前一个命令 linux kernel

Question

within linux kernel source repo, there is Makefile.build under /scripts, which is called many times when building src. there is some target: prerequisite like this:

$(obj)/%.i: $(src)/%.c FORCE
    $(call if_changed_dep,cpp_i_c)

and if_changed_dep is

if_changed_dep = $(if $(newer-prereqs)$(cmd-check),$(cmd_and_fixdep),@:)

newer-prereqs is quite straightforward but cmd-check is a bit obsecure.

cmd-check = $(filter-out $(subst $(space),$(space_escape),$(strip $(cmd_$@))), \
                         $(subst $(space),$(space_escape),$(strip $(cmd_$1))))

I know that $(cmd_$1) will be expanded to cmd_cpp_i_c , which is the current compiling command

and $(cmd_$@) will be expanded to $(cmd_$(obj)/%.i). for instance if it compiles i2c-core-base.c, it will be $(cmd_i2c-core-base.i) (I omit $(obj))

https://flylib.com/books/en/2.860.1.84/1/ says it is the previous command when compiling.

my question is where I am able to find the evidence since I could not find where cmd_$@ is defined.

Thanks a lot for any comments.

Answer 1

After executing the command, the macro cmd_and_savecmd, records the command line into the file..cmd.

In /scripts/Kbuild.include

cmd_and_savecmd =                                                            \
    $(cmd);                                                              \
    printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd

As make is invoked again during a rebuild, it will include those.*.cmd files.

In /Makefile

 -include $(foreach f,$(existing-targets),$(dir $(f)).$(notdir $(f)).cmd)

So, cmd_$@ is used to keep tracks of what command has already been done last time when building a file.