在verilog中是否有一种可综合的方式将IP内部引脚绑定到顶部

Question

I have a IP subsys in my SoC project, there are many sram macro inside it. Based on the sram library, there are some extra pins for sram speed config. I need connect these pins to top of the IP. Is there a synthesizable way to do this in verilog, instead of patch IP RTL code to connect the pins through every hierarchy inside IP.

Answer 1

No, you are going to have to connect the requisite pins up the module hierarchy in order to access the requisite signals from the top level module. In synthesizable SystemVerilog you are only able to instantiate modules, and modules only allow you to access the signals they expose in their ports.